6.2.1. Data cache disabled behaviour

The SCTLR.C bit, see System Control Register, enables or disables the L1 data and unified caches when ACTLR.SMP is 1. When ACTLR.SMP is 0 during the processor power-up and power-down procedures, the caches are disabled regardless of the SCTLR.C bit setting.

When the L1 data and unified caches are disabled, cacheable loads and stores lookup in the caches as normal. On an L1 data cache hit, a load or store proceeds as if the L1 data cache were enabled. On an L1 data cache miss, the cache line is not allocated into the L1 data cache. A cacheable load that misses in both the L1 data and unified caches issues a ReadOnce or ReadNoSnoop transaction on the ACE master interface.

If the L1 data and unified caches are disabled, cache maintenance operations can still execute normally.

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