2.4.4. Communication to the Power Management Controller

Communication between the Cortex-A7 MPCore processor and the system power management controller can be performed using the STANDBYWFI[3:0] and STANDBYWFIL2 signals.

The STANDBYWFI[n] signal indicates when an individual processor is in idle and low power state. The power management controller can remove power from an individual processor when STANDBYWFI[n] is asserted. See Individual processor shutdown mode for more information.

The STANDBYWFIL2 signal indicates when all individual processors and the L2 memory system are in idle and low power state. A power management controller can remove power from the Cortex-A7 MPCore processor when STANDBYWFIL2 is asserted. See Multiprocessor device shutdown mode for more information.

Note

The Cortex-A7 MPCore processor includes a minimal L2 memory system in configurations without an L2 cache. Therefore, the power management controller must always wait for assertion of STANDBYWFIL2 before removing power from the Cortex-A7 MPCore processor.

Figure 2.6 shows how STANDBYWFI[3:0] and STANDBYWFIL2 correspond to individual processors and the Cortex-A7 MPCore processor.

Figure 2.6. STANDBYWFI[3:0] and STANDBYWFIL2 signals

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