3.2. Execution environment support

For the Cortex-A7 MPCore processor, ARM deprecates any use of the ThumbEE instruction set and provides a trivial implementation of the Jazelle Extension.

This means that:

See the ARM Architecture Reference Manual.

Table 3.1 shows the Jazelle register instruction summary and the response to the instructions.

Table 3.1. Jazelle register instruction summary

RegisterInstructionResponse
Jazelle ID (JIDR)[a]MRC p14, 7, <Rd>, c0, c0, 0

Reads as zero[b].

MCR p14, 7, <Rd>, c0, c0, 0

A write causes an undefined exception regardless of processor mode.

Jazelle main configuration (JMCR) [c]MRC p14, 7, <Rd>, c2, c0, 0 Reads as zero[d].
MCR p14, 7, <Rd>, c2, c0, Ignore writes[d].
Jazelle OS control (JOSCR)[e]MRC p14, 7, <Rd>, c1, c0, 0 Reads as zero[d].
MCR p14, 7, <Rd>, c1, c0, 0 Ignore writes[d].

[a] Accessible from all privilege levels.

[b] Can cause a trap to Hyp mode depending on the TID0 bit set in HCR.

[c] Write-only accessible in unprivileged level, read-write accessible at PL1 or higher.

[d] Can cause a trap to Hyp mode depending on the TJDBX bit set in HSTR.

[e] Accessible from PL1 or higher.


Note

Because no hardware acceleration is present in the processor when the BXJ instruction is used the BX instruction is invoked.

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