7.3.1. Memory interface attributes

Table 7.3 shows the ACE master interface attributes for the Cortex-A7 MPCore processor. The table lists the maximum possible values for the read and write issuing capabilities if the processor includes four processors.

Table 7.3. ACE master interface attributes

AttributeValueComments
Write issuing capability33+n[a]

The write issue capability is made up of:

  • 16 Non-cacheable, Device or Strongly-ordered writes[b].

  • 16 Cacheable (either inner or outer) writes.

  • 1 barrier operation for each processor.

1 barrier is generated from the cluster.

Read issuing capability8n[a] + 66

8 for each processor in the multiprocessor device including up to:

  • 5 data linefills.

  • 1 Non-cacheable, Device, or Strongly ordered data read.

  • 1 Non-cacheable TLB page-walk read.

  • 1 instruction fetch, either cacheable linefill or Non-cacheable.

  • 4 coherency operations.

  • 1 barrier operation.

1 barrier operation is generated from the cluster and up to 63 outstanding DVM messages. Up to 2 Level 2 linefills generated by the cluster if L2 is present

Exclusive thread capabilityn[a] Each processor can have 1 exclusive access sequence in progress
Write ID capability3n[a] + 17

The Write ID capability is made up of:

  • 1 for Non-cacheable writes for each processor.

  • 1 for Device or Strongly-ordered writes for each processor.

  • 1 barrier operation for each processor.

  • 1 for barriers across the whole cluster.

  • 16 for cacheable writes across the whole cluster.

Write ID width5The ID encodes the source of the memory transaction. See Table 7.4.
Read ID capability10n[a] + 5

10 for each processor in the multiprocessor device including:

  • 3 for the L2 cache.

  • 1 for DVM messages.

  • 1 for barriers.

If the L2 cache is not present the read ID capability value changes to 10n + 2.

Read ID width6The ID encodes the source of the memory transaction. See Table 7.5.

[a] n is the processor number 1-4.

[b] For a single processor, there is a limit of 15 normal non-cacheable writes


Table 7.4 shows the Encodings for AWIDM[4:0]

Table 7.4. Encodings for AWIDM[4:0]

AttributeValueComments
Write ID0b000nn[a]Processor nn Non-cacheable or STREX
0b001nn[a]Processor nn writes to Device and Strongly-ordered memory
0b010nn[a]Processor nn write portion of the barrier transactions
0b01111Write portion of barrier caused by external DVM synchronization
0b1bbbb[b]Writes to cacheable memory

[a] Where nn is the processor number 0b00, 0b01, 0b10, or 0b11.

[b] Where bbbb is an arbitrary value between 0x0-0xF.


Table 7.5 shows the Encodings for ARIDM[5:0]

Table 7.5. Encodings for ARIDM[5:0]

AttributeValueComments
Read ID0b0000nn[a]Processor nn Non-cacheable, Device or Strongly-ordered, including LDREX
0b0001nn[a]Processor nn TLB
0b0010nn[a]Processor nn read portion of barrier transactions
0b001111Read portion of barrier transaction caused by external DVM synchronization
0b0100nn[a]Processor nn Line-Fill Buffer 0
0b0101nn[a]Processor nn Line-Fill Buffer 1
0b0110nn[a]Processor nn instruction
0b1000nn[a]Processor nn STB0
0b1001nn[a]Processor nn STB1
0b1010nn[a]Processor nn STB2
0b1011nn[a]Processor nn STB3
0b1100nn[a]Processor nn DVM request
0b110100DVM Complete messages
0b111mmm[b]L2 Line-Fill Buffer

[a] Where nn is the processor number 0b00, 0b01, 0b10, or 0b11.

[b] Where mmm is L2 encoding of the Line-Fill Buffer.


See the AMBA AXI and ACE Protocol Specification for more information about the ACE and AXI signals described in this manual.

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