4.2.22. Cache maintenance operations

Table 4.20 shows the cache and branch predictor maintenance operations.

Table 4.20. Cache and branch predictor maintenance operations

NameCRnOp1CRmOp2ResetDescription
ICIALLUISc70c10UNK

Instruction cache invalidate all to PoU[a] Inner Shareable, see the ARM Architecture Reference Manual

BPIALLIS   6UNK

Branch predictor invalidate all Inner Shareable, see the ARM Architecture Reference Manual

ICIALLU  c50UNK

Instruction cache invalidate all to PoU, see the ARM Architecture Reference Manual

ICIMVAU   1UNK

Instruction cache invalidate by MVA to PoU, see the ARM Architecture Reference Manual

BPIALLc70c56UNK

Branch predictor invalidate all, see the ARM Architecture Reference Manual

BPIMVA   7UNK

Branch predictor invalidate by MVA, see the ARM Architecture Reference Manual

DCIMVAC[b]  c61UNK

Data cache invalidate by MVA to PoC[c], see the ARM Architecture Reference Manual

DCISW[d]   2UNK

Data cache invalidate by set/way, see the ARM Architecture Reference Manual

DCCMVAC  c101UNK

Data cache clean by MVA to PoC, see the ARM Architecture Reference Manual

DCCSW   2UNK

Data cache clean by set/way, see the ARM Architecture Reference Manual

DCCMVAU  c111UNK

Data cache clean by MVA to PoU, see the ARM Architecture Reference Manual

DCCIMVAC  c141UNK

Data cache clean and invalidate by MVA to PoC, see the ARM Architecture Reference Manual

DCCISW   2UNK

Data cache clean and invalidate by set/way, see the ARM Architecture Reference Manual

[a] PoU = Point of Unification. PoU is set by the BROADCASTINNER pin and can be in the L1 data cache or outside of the processor, in which case PoU is dependent on the external memory system.

[b] DCIMVAC is upgraded to DCCIMVAC for the individual processor that the DCIMVAC is executed on. Additionally, if the DCIMVAC is executed from a Non-secure state other than Hyp mode without second state write permissions then the DCIMVAC is upgraded to DCCIMVAC when broadcast to other processors or broadcast on the ACE interface.

[c] PoC = Point of Coherence. The PoC is always outside of the processor and is dependent on the external memory system.

[d] DCISW is upgraded to DCCISW when executed in a Non-secure PL1 mode if HCR.SWIO is set to 1.


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