4.2.24. Address translation operations

Table 4.22 shows the address translation register and operations.

Table 4.22. Address translation operations

NameCRnOp1CRmOp2ResetWidthDescription
PARc70c40

UNK

32-bit

Physical Address Register

- c7-64-bit
ATS1CPR  c80UNK32-bit

Stage 1 current state PL1 read, see the ARM Architecture Reference Manual

ATS1CPW   1UNK32-bit

Stage 1 current state PL1 write, see the ARM Architecture Reference Manual

ATS1CURc70c82UNK32-bit

Stage 1 current state unprivileged (PL0) read, see the ARM Architecture Reference Manual

ATS1CUW   3UNK32-bit

Stage 1 current state unprivileged (PL0) write, see the ARM Architecture Reference Manual

ATS12NSOPR   4UNK32-bit

Stages 1 and 2 Non-secure PL1 read, see the ARM Architecture Reference Manual

ATS12NSOPW   5UNK32-bit

Stages 1 and 2 Non-secure PL1 write, see the ARM Architecture Reference Manual

ATS12NSOUR   6UNK32-bit

Stages 1 and 2 Non-secure unprivileged (PL0) read, see the ARM Architecture Reference Manual

ATS12NSOUW   7UNK32-bit

Stages 1 and 2 Non-secure unprivileged (PL0) write, see the ARM Architecture Reference Manual

ATS1HR 4c80UNK32-bit

Stage 1 Hyp mode read, see the ARM Architecture Reference Manual

ATS1HW   1UNK32-bit

Stage 1 Hyp mode write, see the ARM Architecture Reference Manual


Copyright © 2011-2013 ARM. All rights reserved.ARM DDI 0464F
Non-ConfidentialID051113