4.2.26. Performance monitor registers

Table 4.24 shows the performance monitor registers.

Table 4.24. Performance monitor registers

NameCRnOp1CRmOp2ResetDescription
PMCRc90c1200x41072000

Performance Monitor Control Register

PMNCNTENSET   1UNK

Count Enable Set Register, see the ARM Architecture Reference Manual

PMNCNTENCLR   2UNK

Count Enable Clear Register, see the ARM Architecture Reference Manual

PMOVSR   3UNK

Overflow Flag Status Register, see the ARM Architecture Reference Manual

PMSWINC   4UNK

Software Increment Register, see the ARM Architecture Reference Manual

PMSELR   5UNK

Event Counter Selection Register, see the ARM Architecture Reference Manual

PMCEID0   60x3FFF0F3F

Common Event Identification Register 0, see the ARM Architecture Reference Manual

PMCEID1   70x00000000Common Event Identification Register 1, see the ARM Architecture Reference Manual
PMCCNTR  c130UNK

Cycle Count Register, see the ARM Architecture Reference Manual

PMXEVTYPER   1UNK

Event Type Select Register, see the ARM Architecture Reference Manual

PMXEVCNTR   2UNK

Event Count Register, see the ARM Architecture Reference Manual

PMUSERENR  c1400x00000000

User Enable Register, see the ARM Architecture Reference Manual

PMINTENSET1UNK

Interrupt Enable Set Register, see the ARM Architecture Reference Manual

PMINTENCLR2UNK

Interrupt Enable Clear Register, see the ARM Architecture Reference Manual

PMOVSSET3UNK

Performance Monitor Overflow Flag Status Set Register, see the ARM Architecture Reference Manual


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