4.2.19. Virtual memory control registers

Table 4.17 shows the virtual memory control registers.

Table 4.17. Virtual memory control registers

NameCRnOp1CRmOp2ResetWidthDescription
SCTLRc10c000x00C50078[a]32 bit

System Control Register

TTBR0c20c00UNK32 bitTranslation Table Base Register 0, see the ARM Architecture Reference Manual
-0c2-64 bit
TTBR1 0c01UNK32 bitTranslation Table Base Register 1, see the ARM Architecture Reference Manual
-1c2-64 bit
TTBCR 0c02

0x00000000[b]

32 bit

Translation Table Base Control Register, see the ARM Architecture Reference Manual

DACRc30c00UNK32 bit

Domain Access Control Register, see the ARM Architecture Reference Manual

PRRRc100c20UNK32 bitPrimary Region Remap Register
MAIR0   0UNK32 bit

MAIR0 and MAIR1, Memory Attribute Indirection Registers 0 and 1

NMRR   1UNK32 bit

Normal Memory Remap Register

MAIR1   1UNK32 bitMAIR0 and MAIR1, Memory Attribute Indirection Registers 0 and 1
CONTEXTIDRc130c01UNK32 bit

Process ID Register, see the ARM Architecture Reference Manual

[a] The reset value depends on primary inputs, CFGTE, CFGEND, and VINITHI. The value shown in Table 4.17 assumes these signals are set to zero.

[b] The reset value is 0x00000000 for the Secure copy of the register. The reset value for the EAE bit of the Non-secure copy of the register is 0x0. You must program the Non-secure copy of the register with the required initial value, as part of the processor boot sequence.


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