4.2.28. Virtualization Extensions registers

Table 4.26 shows the Virtualization Extensions registers.

Table 4.26. Virtualization Extensions registers

NameCRnOp1CRmOp2ResetWidthDescription
VPIDRc04c00-[a]32-bit

Virtualization Processor ID Registerl

VMPIDR   5-[b]32-bitVirtualization Multiprocessor ID Register
HSCTLRc14c00UNK32-bit

Hyp System Control Register

HACTLR  1UNK Hyp Auxiliary Configuration Register
HCR  c100x0000000032-bit

Hyp Configuration Register, see the ARM Architecture Reference Manual

HDCR   10x00000006[c]32-bit

Hyp Debug Control Register

HCPTR   20x000033FF[d]32-bit

Hyp Coprocessor Trap Register

HSTR   30x0000000032-bit

Hyp System Trap Register, see the ARM Architecture Reference Manual

HTCRc24c02UNK32-bit

Hyp Translation Control Register

VTCR  c12UNK32-bit

Virtualization Translation Control Register, see the ARM Architecture Reference Manual

HTTBR-4c2-UNK64-bit

Hyp Translation Table Base Register, see the ARM Architecture Reference Manual

VTTBR-6c2-UNK[e]64-bit

Virtualization Translation Table Base Register, see the ARM Architecture Reference Manual

HADFSRc54c10UNK32-bit

Hyp Auxiliary Data Fault Status Syndrome Register

HAIFSR   1UNK32-bit

Hyp Auxiliary Instruction Fault Status Syndrome Register

HSR  c20

UNK

32-bitHyp Syndrome Register
HDFARc64c00UNK32-bit

Hyp Data Fault Address Register, see the ARM Architecture Reference Manual

HIFAR   2UNK32-bit

Hyp Instruction Fault Address Register, see the ARM Architecture Reference Manual

HPFAR   4UNK32-bit

Hyp IPA Fault Address Register, see the ARM Architecture Reference Manual

HMAIR0c104c20UNK32-bit

Hyp Memory Attribute Indirection Register 0, see the ARM Architecture Reference Manual

HMAIR1 1UNK32-bit

Hyp Memory Attribute Indirection Register 1, see the ARM Architecture Reference Manual

HAMAIR0c30UNK32-bitHyp Auxiliary Memory Attribute Indirection Register 0
HAMAIR1 1UNK32-bitHyp Auxiliary Memory Attribute Indirection Register 1
HVBARc124c00UNK32-bit

Hyp Vector Base Address Register, see the ARM Architecture Reference Manual

[a] The reset value is the value of the Main ID Register.

[b] The reset value is the value of the Multiprocessor Affinity Register.

[c] The reset value for bit [7] is UNK.

[d] The reset value depends on the FPU and NEON configuration. If FPU and Advanced SIMD are implemented, the reset value is 0x000033FF. If FPU is implemented but Advanced SIMD is not implemented, the reset value is 0x0000B3FF. If FPU and Advanced SIMD are not implemented, the reset value is 0x0000BFFF.

[e] The reset value for bits [54:48] is 0b00000000.


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