5.2.1. Memory types and attributes

Although various different memory types can be specified in the page tables, the Cortex-A7 MPCore processor does not implement all possible combinations:

The attribute behavior for Strongly-ordered and Device memory types are architecturally-defined, see the See the ARM Architecture Reference Manual for more information.

Table 5.1 shows the C, B, and TEX[2:0] encodings for Short-descriptor format memory region without TEX remapping.

Table 5.1. TEX, C, and B encodings when SCTRL.TRE is set to 0

TEX[2:0]CBDescription Memory typePage Shareable
00000Strongly-orderedStrongly-orderedShareable
1Shareable Device DeviceShareable
10Outer and Inner Write-Through, no Write-AllocateNormalS bit [a]
1Outer and Inner Write-Back, no Write-AllocateNormalS bit [a]
00100Outer and Inner Non-cacheableNormalS bit [a]
1Reserved--
10[b]Outer and Inner Write-Back, Write-AllocateNormalS bit [a]
1
01000Non-shareable Device DeviceNon-shareable
1Reserved--
1xReserved--
011xxReserved--
1BBAACacheability[c]

AA = Inner attribute

BB = Outer attribute

NormalS bit [a]

[a] The S bit selects outer shareability. It is not possible to specify inner shareability when TEX remap is set to 0.

[b] For architectural compatibility with other processors, ARM recommends that this encoding is not used.

[c] See the ARM Architecture Reference Manual for more information on cacheability attributes.


Table 5.2 shows the C, B, and TEX[2:0] encodings for Short-descriptor format memory region with TEX remapping.

Table 5.2. TEX, C, and B encodings when SCTRL.TRE is set to 1

EncodingMemory type [a]Cache attributes [a], [b]:Outer Shareable attribute [a], [c]
TEX[0]CBInner cacheOuter cache
000PRRR[1:0]NMRR[1:0]NMRR[17:16]NOT(PRRR[24])
1PRRR[3:2]NMRR[3:2]NMRR[19:18]NOT(PRRR[25])
10PRRR[5:4]NMRR[5:4]NMRR[21:20]NOT(PRRR[26])
1PRRR[7:6]NMRR[7:6]NMRR[23:22]NOT(PRRR[27])
100PRRR[9:8]NMRR[9:8]NMRR[25:24]NOT(PRRR[28])
1PRRR[11:10]NMRR[11:10]NMRR[27:26]NOT(PRRR[29])
10PRRR[13:12]NMRR[13:12]NMRR[29:28]NOT(PRRR[30])
1PRRR[15:14]NMRR[15:14]NMRR[31:30]NOT(PRRR[31])

[a] For details of the Memory type and Outer Shareable encodings see Primary Region Remap Register.

[b] Applies only if the memory type for the region is mapped as Normal memory.

[c] Applies only if the memory type for the region is mapped as Normal or Device memory and the region is Shareable.


Copyright © 2011-2013 ARM. All rights reserved.ARM DDI 0464F
Non-ConfidentialID051113