7.5. AXI privilege information

AXI provides information about the privilege level of an access on the ARPROTM[2:0] and AWPROTM[2:0] signals. However, when accesses might be cached or merged together, the resulting transaction can have both privileged and user data combined. If this happens, the Cortex-A7 MPCore processor marks the transaction as privileged, even it if was initiated by a user process.

Table 7.7 shows Cortex-A7 MPCore processor modes and corresponding ARPROTM[2:0] and AWPROTM[2:0] values.

Table 7.7. Cortex-A7 MPCore mode and ARPROT and AWPROT values

Processor modeType of access

Value of ARPROT[0] and AWPROT[0]

PL0, PL1, PL2Cacheable read accessPrivileged access
PL0Device, Strongly-ordered, or normal Non-cacheable read accessNormal access
PL1, PL2Privileged access
PL0, PL1, PL2Cacheable write accessPrivileged access
PL0Device or Strongly-ordered write Normal access
PL1, PL2Privileged access
PL0Normal Non-cacheable write, except for STREX, STREXB, STREXH, and STREXD to shareable memoryPrivileged access
PL0Normal Non-cacheable write for STREX, STREXB, STREXH, and STREXD to shareable memoryNormal access
PL1, PL2Normal Non-cacheable write Privileged access
PL0, PL1, PL2TLB pagewalk Privileged access

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