1.7.2. Design flow

The Cortex-A7 MPCore processor is delivered as synthesizable Verilog RTL. Before it can be used in a product, it must go through the following process:


The implementer configures and synthesizes the RTL to produce a hard macrocell. This might include integrating the RAMs into the design.


The integrator connects the implemented design into a SoC. This includes connecting it to a memory system and peripherals.


The system programmer develops the software required to configure and initialize the processor, and tests the required application software.

Each stage of the process:

The operation of the final device depends on:

Build configuration

The implementer chooses the options that affect how the RTL source files are pre-processed. They usually include or exclude logic that can affect the area or maximum frequency of the resulting macrocell.

Configuration inputs

The integrator configures some features of the processor by tying inputs to specific values. These configurations affect the start-up behavior before any software configuration is made. They can also limit the options available to the software.

Software configuration

The programmer configures the processor by programming particular values into software-visible registers. This affects the behavior of the processor.


This manual refers to implementation-defined features that are applicable to build configuration options. References to a feature that is included means that the appropriate build and pin configuration options have been selected, while references to an enabled feature means one that has also been configured by software.

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