7.2.1. ACE configuration signals

The Cortex-A7 MPCore processor implements the following ACE configuration signals:

Table 7.1 shows the permitted combinations of these signals and the supported configurations in the Cortex-A7 MPCore processor.

Table 7.1. Supported ACE configurations

  Feature
SignalAXI3 mode[a]ACE non-coherent[b] ACE outer coherent ACE inner coherent
  

No L3 Cache

With L3 Cache

No L3 Cache

With L3 Cache

No L3 Cache

With L3 Cache

BROADCASTCACHEMAINT0010101
BROADCASTOUTER0001111
BROADCASTINNER0000011

[a] SYSBARDISABLE must be set to 1 in AXI3 mode.

[b] ACE non-coherent is compatible with connecting to an ACE-Lite interconnect.


Table 7.2 shows the key features in each of the supported ACE configurations.

Table 7.2. Supported features in the ACE configurations

FeaturesConfiguration   
AXI3 modeACE non-coherent, no L3 cacheACE non-coherent, with L3 cacheACE outer coherentACE inner coherent
AXI3 complianceYNNNN
ACE complianceNYYYY
Barriers on AR and AW channelsNYYYY
Cache maintenance requests on AR channelNNYYY
Snoops on AC channelNNNYY
Coherent requests on AR or AW channelNNNYY
DVM requests on AR channelNNNNY

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