7.3.3. ACE channel properties

Table 7.6 show the properties of the ACE channels.

Table 7.6. ACE channel properties

Snoop acceptance capability6The SCU can accept and process a maximum of six snoop requests from the system.
Snoop latencyHit

When there is a hit in L2 cache, the best case for response and data is eight processor cycles. When there is a miss in L2 cache and a hit in L1 cache, the best case for response and data is ten processor cycles.


Latencies can be higher if hazards occur or if there are not enough buffers to absorb requests.

MissBest case six processor cycles as the SCU duplicate tags and L2 tags indicate the miss.

The multiprocessor device takes:

  • Three cycles to provide an AC-CR response to non-DVM synchronization packets providing that there are no ongoing snoops in to a processor.

  • Minimum of six cycles to provide a CR-AR response to DVM synchronization packets.

Snoop filter SupportedThe multiprocessor device provides support for an external snoop filter in an interconnect. It indicates when clean lines are evicted from the processor by sending Evict transactions on the ACE write channel. However there are some cases where incorrect software can prevent an Evict transaction from being sent, therefore you must ensure that any external snoop filter is built to handle a capacity overflow that sends a back-invalidation to the processor if it runs out of storage.
Supported transactions-

All transactions described by the ACE protocol:

  • Are accepted on the ACE master interface from the system.

  • Can be produced on the ACE master interface except:

    • WriteUnique

    • WriteLineUnique

    • ReadNotSharedDirty

    • MakeUnique.

DVM issue63DVM messages, except for DVM synchronization, can be issued back-to-back continuously as Cortex-A7 MPCore processor does not require a response from the interconnect fabric to retire a single DVM message or multi-part DVM messages.

See the AMBA AXI and ACE Protocol Specification for more information about the ACE channel.

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