Cortex™-A7 MPCore™ Technical Reference Manual

Revision: r0p5


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Glossary
Conventions
Additional reading
Feedback
Feedback on this product
Feedback on content
1. Introduction
1.1. About the Cortex-A7 MPCore processor
1.2. Compliance
1.2.1. ARM architecture
1.2.2. Advanced Microcontroller Bus Architectures
1.2.3. Debug architecture
1.2.4. Generic Interrupt Controller architecture
1.2.5. Generic Timer architecture
1.3. Features
1.4. Interfaces
1.5. Configurable options
1.6. Test features
1.7. Product documentation and design flow
1.7.1. Documentation
1.7.2. Design flow
1.8. Product revisions
2. Functional Description
2.1. About the Cortex-A7 MPCore processor functions
2.1.1. Processor components
2.2. Interfaces
2.2.1. ACE
2.2.2. APB
2.2.3. ETM
2.2.4. DFT
2.2.5. MBIST controller
2.3. Clocking and resets
2.3.1. Clocking
2.3.2. Resets
2.4. Power management
2.4.1. Power domains
2.4.2. Power modes
2.4.3. Event communication using WFE or SEV
2.4.4. Communication to the Power Management Controller
3. Programmers Model
3.1. About the programmers model
3.2. Execution environment support
3.3. Advanced SIMD and VFP Extensions
3.4. Security Extensions architecture
3.4.1. System boot sequence
3.4.2. Security Extensions write access disable
3.5. Virtualization Extensions architecture
3.6. Large Physical Address Extension architecture
3.7. Multiprocessing Extensions
3.8. Modes of operation
3.9. Memory model
4. System Control
4.1. About system control
4.2. Register summary
4.2.1. c0 registers
4.2.2. c1 registers
4.2.3. c2 registers
4.2.4. c3 registers
4.2.5. c4 registers
4.2.6. c5 registers
4.2.7. c6 registers
4.2.8. c7 registers
4.2.9. c8 registers
4.2.10. c9 registers
4.2.11. c10 registers
4.2.12. c11 registers
4.2.13. c12 registers
4.2.14. c13 registers
4.2.15. c14 registers
4.2.16. c15 registers
4.2.17. 64-bit registers
4.2.18. Identification registers
4.2.19. Virtual memory control registers
4.2.20. PL1 Fault handling registers
4.2.21. Other system control registers
4.2.22. Cache maintenance operations
4.2.23. TLB maintenance operations
4.2.24. Address translation operations
4.2.25. Miscellaneous operations
4.2.26. Performance monitor registers
4.2.27. Security Extensions registers
4.2.28. Virtualization Extensions registers
4.2.29. TLB maintenance operations
4.2.30. Generic Timer registers
4.2.31. Implementation defined registers
4.3. Register descriptions
4.3.1. Main ID Register
4.3.2. Cache Type Register
4.3.3. TCM Type Register
4.3.4. TLB Type Register
4.3.5. Multiprocessor Affinity Register
4.3.6. Revision ID Register
4.3.7. Processor Feature Register 0
4.3.8. Processor Feature Register 1
4.3.9. Debug Feature Register 0
4.3.10. Auxiliary Feature Register 0
4.3.11. Memory Model Feature Register 0
4.3.12. Memory Model Feature Register 1
4.3.13. Memory Model Feature Register 2
4.3.14. Memory Model Feature Register 3
4.3.15. Instruction Set Attribute Register 0
4.3.16. Instruction Set Attribute Register 1
4.3.17. Instruction Set Attribute Register 2
4.3.18. Instruction Set Attribute Register 3
4.3.19. Instruction Set Attribute Register 4
4.3.20. Instruction Set Attribute Register 5
4.3.21. Cache Size ID Register
4.3.22. Cache Level ID Register
4.3.23. Auxiliary ID Register
4.3.24. Cache Size Selection Register
4.3.25. Virtualization Processor ID Register
4.3.26. Virtualization Multiprocessor ID Register
4.3.27. System Control Register
4.3.28. Primary Region Remap Register
4.3.29. MAIR0 and MAIR1, Memory Attribute Indirection Registers 0 and 1
4.3.30. Normal Memory Remap Register
4.3.31. Auxiliary Control Register
4.3.32. Coprocessor Access Control Register
4.3.33. Secure Configuration Register
4.3.34. Non-Secure Access Control Register
4.3.35. Hyp System Control Register
4.3.36. Hyp Auxiliary Configuration Register
4.3.37. Hyp Debug Control Register
4.3.38. Hyp Coprocessor Trap Register
4.3.39. Hyp Auxiliary Configuration Register
4.3.40. Hyp Translation Control Register
4.3.41. Data Fault Status Register
4.3.42. Instruction Fault Status Register
4.3.43. Auxiliary Data Fault Status Register
4.3.44. Auxiliary Instruction Fault Status Register
4.3.45. Hyp Auxiliary Data Fault Status Syndrome Register
4.3.46. Hyp Auxiliary Instruction Fault Status Syndrome Register
4.3.47. Hyp Syndrome Register
4.3.48. Physical Address Register
4.3.49. L2 Control Register
4.3.50. L2 Extended Control Register
4.3.51. Auxiliary Memory Attribute Indirection Register 0
4.3.52. Auxiliary Memory Attribute Indirection Register 1
4.3.53. Hyp Auxiliary Memory Attribute Indirection Register 0
4.3.54. Hyp Auxiliary Memory Attribute Indirection Register 1
4.3.55. FCSE Process ID Register
4.3.56. Configuration Base Address Register
5. Memory Management Unit
5.1. About the MMU
5.2. Memory management system
5.2.1. Memory types and attributes
5.3. TLB organization
5.3.1. Micro TLB
5.3.2. Main TLB
5.3.3. IPA cache RAM
5.3.4. Walk cache RAM
5.4. TLB match process
5.5. Memory access sequence
5.6. MMU enabling and disabling
5.7. External aborts
5.7.1. External aborts on data write
5.7.2. External aborts on data read
5.7.3. Synchronous and asynchronous aborts
5.8. MMU software accessible registers
6. L1 Memory System
6.1. About the L1 memory system
6.2. Cache behavior
6.2.1. Data cache disabled behaviour
6.2.2. Instruction cache disabled behavior
6.2.3. Instruction cache speculative memory accesses
6.3. L1 instruction memory system
6.3.1. Enabling program flow prediction
6.3.2. Program flow prediction
6.4. L1 data memory system
6.4.1. Internal exclusive monitor
6.4.2. ACE transactions
6.5. Data prefetching
6.5.1. PLD and PLDW instructions
6.5.2. Data prefetching and monitoring
6.6. Direct access to internal memory
6.6.1. Data cache tag and data encoding
6.6.2. Instruction cache tag and data encoding
6.6.3. TLB RAM accesses
7. L2 Memory System
7.1. About the L2 Memory system
7.2. Snoop Control Unit
7.2.1. ACE configuration signals
7.3. Master interface
7.3.1. Memory interface attributes
7.3.2. ACE transfers
7.3.3. ACE channel properties
7.3.4. AXI transaction IDs
7.3.5. Write response
7.3.6. AXI3 Compatibility mode
7.4. Optional integrated L2 cache
7.4.1. External aborts handling
7.5. AXI privilege information
8. Generic Interrupt Controller
8.1. About the GIC
8.2. GIC functional description
8.2.1. GIC memory-map
8.2.2. Interrupt sources
8.2.3. Interrupt priority formats
8.2.4. GIC configuration
8.3. GIC programmers model
8.3.1. Distributor register summary
8.3.2. Distributor register descriptions
8.3.3. CPU Interface register summary
8.3.4. CPU Interface register descriptions
8.3.5. Virtual interface control register summary
8.3.6. Virtual Interface Control Register description
8.3.7. Virtual CPU interface register summary
8.3.8. Virtual CPU interface register description
9. Generic Timer
9.1. About the Generic Timer
9.2. Generic timer functional description
9.3. Timer programmers model
10. Debug
10.1. About debug
10.1.1. Debug host
10.1.2. Protocol converter
10.1.3. Debug target
10.1.4. The debug unit
10.2. Debug register interfaces
10.2.1. Processor interfaces
10.2.2. Breakpoints and watchpoints
10.2.3. Effects of resets on debug registers
10.3. Debug register summary
10.4. Debug register descriptions
10.4.1. Debug Identification Register
10.4.2. Program Counter Sampling Register
10.4.3. Debug Run Control Register
10.4.4. Debug External Auxiliary Control Register
10.4.5. Breakpoint Value Registers
10.4.6. Breakpoint Control Registers
10.4.7. Watchpoint Value Registers
10.4.8. Watchpoint Control Registers
10.4.9. Debug ROM Address Register
10.4.10. Breakpoint Extended Value Registers
10.4.11. OS Lock Access Register
10.4.12. OS Lock Status Register
10.4.13. Device Power-down and Reset Control Register
10.4.14. Debug Self Address Offset Register
10.4.15. Integration Miscellaneous Signals Register
10.4.16. Integration Miscellaneous Signals Input Register
10.4.17. Integration Mode Control Register
10.4.18. Claim Tag Set Register
10.4.19. Claim Tag Clear Register
10.4.20. Debug Device ID Register 1
10.4.21. Debug Device ID Register
10.4.22. Debug Peripheral Identification Registers
10.4.23. Debug Component Identification Registers
10.5. Debug events
10.5.1. Watchpoint debug events
10.5.2. Asynchronous aborts
10.6. External debug interface
10.6.1. Memory map
10.6.2. Changing the authentication signals
11. Performance Monitoring Unit
11.1. About the Performance Monitoring Unit
11.2. PMU functional description
11.2.1. Event interface
11.2.2. CP15 and APB interface
11.2.3. Counters
11.3. PMU registers summary
11.4. PMU register descriptions
11.4.1. Performance Monitor Control Register
11.4.2. Performance Monitors Peripheral Identification Registers
11.4.3. Performance Monitors Component Identification Registers
11.5. Events
11.6. Interrupts
11.7. Exporting PMU events
11.7.1. External hardware
11.7.2. Debug trace hardware
A. Signal Descriptions
A.1. About the signal descriptions
A.2. Clock and reset signals
A.3. Configuration signals
A.4. Generic Interrupt Controller signals
A.5. Generic timer signals
A.6. Power control signals
A.7. ACE master interface signals
A.7.1. Clock and configuration signals
A.7.2. Asynchronous error signals
A.7.3. Write address channel signals
A.7.4. Write data channel signals
A.7.5. Write data response channel signals
A.7.6. Read address channel signals
A.7.7. Read data channel signals
A.7.8. Snoop address channel signals
A.7.9. Snoop response channel signals
A.7.10. Snoop data channel signals
A.7.11. Read/write acknowledge signals
A.8. External debug interface
A.8.1. APB Interface signals
A.8.2. Authentication interface signals
A.8.3. Miscellaneous Debug signals
A.8.4. ETM interface signals
A.8.5. PMU signals
A.9. DFT and MBIST interface signals
A.9.1. DFT interface
A.9.2. MBIST interface
B. Revisions

List of Figures

1. Key to timing diagram conventions
1.1. Example multiprocessor configuration
2.1. Cortex-A7 MPCore processor top-level diagram
2.2. ACLKENM with CLKIN:ACLKM ratio changing from 3:1 to 1:1
2.3. Power domains
2.4. STANDBYWFI deassertion timing
2.5. L2 Wait For Interrupt timing
2.6. STANDBYWFI[3:0] and STANDBYWFIL2 signals
4.1. MIDR bit assignments
4.2. CTR bit assignments
4.3. TLBTR bit assignments
4.4. MPIDR bit assignments
4.5. REVIDR bit assignments
4.6. ID_PFR0 bit assignments
4.7. ID_PFR1 bit assignments
4.8. ID_DFR0 bit assignments
4.9. ID_MMFR0 bit assignments
4.10. ID_MMFR1 bit assignments
4.11. ID_MMFR2 bit assignments
4.12. ID_MMFR3 bit assignments
4.13. ID_ISAR0 bit assignments
4.14. ID_ISAR1 bit assignments
4.15. ID_ISAR2 bit assignments
4.16. ID_ISAR3 bit assignments
4.17. ID_ISAR4 bit assignments
4.18. CCSIDR bit assignments
4.19. CLIDR bit assignments
4.20. CSSELR bit assignments
4.21. VPIDR bit assignments
4.22. VMPIDR bit assignments
4.23. SCTLR bit assignments
4.24. PRRR bit assignments
4.25. MAIR0 and MAIR1 bit assignments
4.26. NMRR bit assignments
4.27. ACTLR bit assignments
4.28. CPACR bit assignments
4.29. SCR bit assignments
4.30. NSACR bit assignments
4.31. HSCTLR bit assignments
4.32. HDCR bit assignments
4.33. HCPTR bit assignments
4.34. DFSR bit assignments for Short-descriptor translation table format
4.35. DFSR bit assignments for Long-descriptor translation table format
4.36. IFSR bit assignments for Short-descriptor translation table format
4.37. IFSR bit assignments for Long-descriptor translation table format
4.38. HSR bit assignments
4.39. L2CTLR bit assignments
4.40. L2ECTLR bit assignments
4.41. CBAR bit assignments
8.1. GICD_TYPER bit assignments
8.2. GICD_IIDR bit assignments
8.3. GICD_PPISR bit assignments
8.4. GICD_SPISRn bit assignments
8.5. GICD_SPISRn address map
8.6. GICC_IIDR bit assignments
8.7. GICH_VTR bit assignments
10.1. Typical debug system
10.2. DBGDIDR bit assignments
10.3. DBGPCSR bit assignments
10.4. DBGDRCR bit assignments
10.5. DBGEACR bit assignments
10.6. DBGBVR bit assignments
10.7. DBGBCR bit assignments
10.8. DBGWVR bit assignments
10.9. DBGWCR bit assignments
10.10. DBGDRAR 32-bit assignments
10.11. DBGDRAR 64-bit assignments
10.12. DBGBXVR bit assignments
10.13. DBGOSLAR bit assignments
10.14. DBGOSLSR bit assignments
10.15. DBGPRCR bit assignments
10.16. DBGDSAR 32-bit assignments
10.17. DBGDSAR 64-bit assignments
10.18. DBGITMISCOUT bit assignments
10.19. DBGITMISCIN bit assignments
10.20. DBGITCTRL bit assignments
10.21. DBGCLAIMSET bit assignments
10.22. DBGCLAIMCLR bit assignments
10.23. DBGDEVID1 bit assignments
10.24. DBGDEVID bit assignments
10.25. External debug interface, including APBv3 slave port
11.1. PMU block diagram
11.2. Performance Monitor Control Register bit assignments

List of Tables

1.
1.1. Configurable options for the Cortex-A7 MPCore RTL
2.1. Valid reset combinations
2.2. Supported power modes
3.1. Jazelle register instruction summary
3.2. CPSR J and T bit encoding
4.1. System control register field values
4.2. c0 register summary
4.3. c1 register summary
4.4. c2 register summary
4.5. c3 register summary
4.6. c5 register summary
4.7. c6 register summary
4.8. c7 register summary
4.9. c8 register summary
4.10. c9 register summary
4.11. c10 register summary
4.12. c10 register summary
4.13. c13 register summary
4.14. c15 register summary
4.15. 64-bit register summary
4.16. Identification registers
4.17. Virtual memory control registers
4.18. PL1 Fault handling registers
4.19. Other system control registers
4.20. Cache and branch predictor maintenance operations
4.21. TLB maintenance operations
4.22. Address translation operations
4.23. Miscellaneous system control operations
4.24. Performance monitor registers
4.25. Security Extensions registers
4.26. Virtualization Extensions registers
4.27. TLB maintenance operations
4.28. Memory access registers
4.29. MIDR bit assignments
4.30. CTR bit assignments
4.31. TLBTR bit assignments
4.32. MPIDR bit assignments
4.33. REVIDR bit assignments
4.34. ID_PFR0 bit assignments
4.35. ID_PFR1 bit assignments
4.36. ID_DFR0 bit assignments
4.37. ID_MMFR0 bit assignments
4.38. ID_MMFR1 bit assignments
4.39. ID_MMFR2 bit assignments
4.40. ID_MMFR3 bit assignments
4.41. ID_ISAR0 bit assignments
4.42. ID_ISAR1 bit assignments
4.43. ID_ISAR2 bit assignments
4.44. ID_ISAR3 bit assignments
4.45. ID_ISAR4 bit assignments
4.46. CCSIDR bit assignments
4.47. CCSIDR encodings
4.48. CLIDR bit assignments
4.49. CSSELR bit assignments
4.50. VPIDR bit assignments
4.51. VMPIDR bit assignments
4.52. SCTLR bit assignments
4.53. PRRR bit assignments
4.54. Memory attributes and the n value for the PRRR field descriptions
4.55. MAIR0 and MAIR1 bit assignments
4.56. MAIRn.Attrm[7:4] encoding
4.57. MAIRn.Attrm[3:0] encoding
4.58. Encoding of R and W bits in some Attrm fields
4.59. NMRR bit assignments
4.60. ACTLR bit assignments
4.61. CPACR bit assignments
4.62. SCR bit assignments
4.63. NSACR bit assignments
4.64. HSCTLR bit assignments
4.65. HDCR bit assignments
4.66. HCPTR bit assignments
4.67. DFSR bit assignments for Short-descriptor translation table format
4.68. DFSR bit assignments for Long-descriptor translation table format
4.69. Encodings of LL bits associated with the MMU fault
4.70. IFSR bit assignments for Long-descriptor translation table format
4.71. IFSR bit assignments for Long-descriptor translation table format
4.72. Encodings of LL bits associated with the MMU fault
4.73. HSR bit assignments
4.74. L2CTLR bit assignments
4.75. L2ECTLR bit assignments
4.76. CBAR bit assignments
5.1. TEX, C, and B encodings when SCTRL.TRE is set to 0
5.2. TEX, C, and B encodings when SCTRL.TRE is set to 1
5.3. CP15 register functions
6.1. ACE transactions
6.2. Cortex-A7 MPCore system coprocessor CP15 registers used to access internal memory
6.3. Data cache tag and data location encoding
6.4. Data cache tag data format
6.5. Instruction cache tag and data location encoding
6.6. Instruction cache tag data format
6.7. TLB Data Read Operation Register location encoding
6.8. TLB RAM format
6.9. Main TLB descriptor data fields
6.10. Walk cache descriptor fields
6.11. IPA cache descriptor fields
7.1. Supported ACE configurations
7.2. Supported features in the ACE configurations
7.3. ACE master interface attributes
7.4. Encodings for AWIDM[4:0]
7.5. Encodings for ARIDM[5:0]
7.6. ACE channel properties
7.7. Cortex-A7 MPCore mode and ARPROT and AWPROT values
8.1. GIC memory map
8.2. GIC configurable options
8.3. Distributor register summary
8.4. GICD_TYPER bit assignments
8.5. GICD_IIDR bit assignments
8.6. GICD_PPISR bit assignments
8.7. GICD_SPISRn bit assignments
8.8. CPU Interface register summary
8.9. Active Priority Register implementation
8.10. GICC_IIDR bit assignments
8.11. Virtual interface control register summary
8.12. GICH_VTR bit assignments
8.13. Virtual CPU interface register summary
9.1. System Timer registers
10.1. CP14 debug register summary
10.2. DBGDIDR bit assignments
10.3. DBGPCSR bit assignments
10.4. DBGDRCR bit assignments
10.5. DBGEACR bit assignments
10.6. DBGBVR bit assignments when register is used for address comparison
10.7. DBGBVR bit assignments when register is used for Context ID comparison
10.8. DBGBCR bit assignments
10.9. DBGWVR bit assignments
10.10. DBGWCR bit assignments
10.11. DBGDRAR bit assignments
10.12. DBGBXVR bit assignments
10.13. DBGOSLAR bit assignments
10.14. DBGOSLSR bit assignments
10.15. DBGPRCR bit assignments
10.16. DBGDSAR bit assignments
10.17. DBGITMISCOUT bit assignments
10.18. DBGITMISCIN bit assignments
10.19. DBGITCTRL bit assignments
10.20. DBGCLAIMSET bit assignments
10.21. DBGCLAIMCLR bit assignments
10.22. DBGDEVID1 bit assignments
10.23. DBGDEVID bit assignments
10.24. Summary of the Debug Peripheral Identification Registers
10.25. Summary of the Component Identification Registers
10.26. Address mapping for debug trace components
11.1. PMU register summary
11.2. PMCR bit assignments
11.3. Summary of the Performance Monitors Peripheral Identification Registers
11.4. Summary of the Performance Monitors Component ID Registers
11.5. Performance monitor events
A.1. Clock and reset signals
A.2. Configuration signals
A.3. GIC signals
A.4. Generic timer signals
A.5. Power control signals
A.6. Clock and configuration signals
A.7. Asynchronous error signals
A.8. address channel signals
A.9. Write data channel signals
A.10. Write data response channel signals
A.11. Read address channel signals
A.12. Read data channel signals
A.13. Snoop address channel signals
A.14. Snoop response channel signals
A.15. Snoop data channel signals
A.16. Read/write acknowledge signals
A.17. APB Interface signals
A.18. Authentication interface signals
A.19. Miscellaneous Debug signals
A.20. ETM interface signals
A.21. Performance Monitoring Unit signals
A.22. DFT interface signals
A.23. MBIST interface signals
B.1. Issue A
B.2. Differences between issue A and issue B
B.3. Differences between issue B and issue C
B.4. Differences between issue C and issue D
B.5. Differences between issue D and issue E
B.6. Differences between issue E and issue F

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Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A03 October 2011First release for r0p0
Revision B09 November 2011First release for r0p1
Revision C11 January 2012First release for r0p2
Revision D15 May 2012First release for r0p3
Revision E19 November 2012First release for r0p4
Revision F11 April 2013First release for r0p5
Copyright © 2011-2013 ARM. All rights reserved.ARM DDI 0464F
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