2.2.3. Memory access

The DMC-400 connects to the system through one or more ACE-Lite interfaces. The DMC-400 supports all the features of the ACE-Lite specification. The features include:


The DMC-400 maps the ACE-Lite system address to a physical DRAM address. The DRAM address consists of a bank number, a row number, and a column number. The DMC-400 supports configurable and programmable controls for mapping the ACE-Lite system address to the physical DRAM address.


DRAM devices have page sizes of 1KB, 2KB, or 4KB. The ACE-Lite protocol does not permit a transaction to cross a 4KB boundary.

The DMC-400 provides programmable controls to map the system address onto the physical chips and channels.

Burst control

The DMC-400 formats all ACE-Lite transactions into memory bursts.

The DMC-400 supports sequential burst addressing and sequential wrapped burst addressing of the DRAM.


The DMC-400 always responds to an ACE-Lite access with an OKAY, EXOKAY, or a DECERR response. It never issues a SLVERR response.

Exclusive access

The DMC-400 provides eight exclusive access monitors for each memory interface. It tracks exclusive accesses at a granularity of the configured DMC-400 burst.

Barriers and cache maintenance operations

The DMC-400 supports barriers and cache maintenance operations to guarantee the correct ordering of memory accesses.

QoS signals

To determine the quality of service value that the system requests for its memory access, the DMC-400 uses the arqos and awqos signals of the ACE-Lite address.

Error-correcting code

The DMC-400 provides SECDED code protection for 32-bit and 64-bit SDRAM interface accesses. It combines the codes with the data of write transactions, and checks the codes for data read transactions.

The DMC-400 uses a programmable interrupt to report the data errors that it corrects. You can read the information of a transaction that the DMC-400 corrects through an APB register in the DMC-400. You can clear the interrupt through an APB register.

The DMC-400 reports uncorrected errors through another programmable interrupt. You can clear the interrupt through an APB register. You can read the information of the transaction through an APB register.

If either interrupt overflows the interrupt system, the DMC-400 triggers another interrupt to notify you that this has happened. You can clear this interrupt through an APB register.

Copyright © 2011-2013 ARM. All rights reserved.ARM DDI 0466D