2.1.5. Clocks and resets

Table 2.2 shows the clock and reset signals of the DMC-400 when you configure it to have the maximum number of system interfaces, and the maximum number of memory interfaces.

Table 2.2. Clock and reset signals

Signal nameWidthDirectionDescription
dmc_clk1InputClock for the DMC-400
pclk1InputClock for the APB interface clock domain
dmc_resetn1InputReset for the DMC-400
presetn1InputReset for APB interface domain


The DMC-400 clock and the APB interface clock must be phase-aligned and synchronous. The DMC-400 clock must run at a frequency higher than, or equal to the frequency of the APB clock. If you want the APB interface to run at a slower rate than dmc_clk, you can reduce the pclk rate using pclken.


You must only change the frequency of the DMC-400 clock when both of the following conditions are true:

  • all memory chips are in self-refresh state or in Deep Power Down (DPD) state

  • the DMC-400 status registers indicate that the memory interface is in the quiescent state.


Use the dmc_resetn signal to reset the DMC-400. You must assert it for longer than two dmc_clk clock periods. You can assert dmc_resetn asynchronously to dmc_clk. You must deassert dmc_resetn synchronously with the rising edge of dmc_clk.

Use the presetn signal to reset the APB interface of the DMC-400. You must assert the presetn signal for longer than two pclk clock periods. You can assert presetn asynchronously to pclk. You must deassert presetn synchronously with the rising edge of pclk.


To assert any DMC-400 reset signal you must set it LOW.

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