A.1. System clock, reset and DFT signals

Table A.1 shows the clock, reset and DFT signals for the DMC-400. The DMC-400 also uses clock and reset signals for the programmers view. See APB signals.

Table A.1. System clock, reset and DFT signals

Signal

Type

Description

dmc_clkInputMain clock source for DMC-400
dmc_resetnInputMain reset for DMC-400
dftseInputDFT scan enable
rst_bypassInputDFT reset bypass

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