A.6. DFI signals

Table A.7 shows the DFI signals. See the DDR PHY Interface (DFI) Specification.

Table A.7. DFI interface signals

Signal

Type

Description

dfi_rddata_valid[a]

Input

Read data valid indicator. The PHY asserts the dfi_rddata_valid signal with the read data for the number of cycles that it sends the read data. The timing is the same as for the dfi_rddata bus.

dfi_rddata[a]

Input

Read data bus. The DMC-400 expects to receive read data from the PHY within tphy_rdlat cycles after it asserts the dfi_rddata_en signal.

dfi_rdecc

Input

Read data ECC code bus. The timing is the same as for the dfi_rddata bus.

dfi_rddata_en[a]

Output

Read data enable. The DMC-400 must assert the dfi_rddata_en signal trddata_en cycles after it asserts the read command on the DFI control interface. It must remain valid for the duration of contiguous read data on the dfi_rddata bus.

dfi_rdecc_en

Output

Read data ECC code enable. The timing is the same as the dfi_rddata_en bus.

dfi_ras_n

Output

DFI row address strobe bus. These signals define the RAS information for all control commands to the DRAM devices.

dfi_cas_n

Output

DFI column address strobe bus. These signals define the CAS information for all control commands to the DRAM devices.

dfi_we_n

Output

DFI write enable bus. These signals define the WEN information for all control commands to the DRAM devices.

dfi_cke[a]

Output

DFI clock enable bus. These signals define the CKE information for all control commands to the DRAM devices.

dfi_cs_n

Output

DFI chip-select bus. These signals define the chip-select information for all control commands to the DRAM devices.
dfi_wrdata_cs_nOutputPHY write training chip-select. Indicates which DRAM chip is being trained.
dfi_rddata_cs_nOutputPHY read training chip-select. Indicates which DRAM chip is being trained.

dfi_cmd_addr

Output

DFI command/address bus. These signals define the CA information for the DRAM memory devices with multiplexed CA signalling, for example LPDDR2.

dfi_address

Output

DFI address bus. These signals define the address information for all control commands to the DRAM memory devices.

dfi_bank

Output

DFI bank bus. These signals define the bank information for all control commands to the DRAM devices.

dfi_odt[a]

Output

DFI on-die termination control bus. These signals define the ODT information for all control commands to the DRAM devices.

dfi_wrdata[a]

Output

Write data bus. The write data stream must begin tphy_wrdata cycles after the DMC-400 asserts the dfi_wrdata_en signal and continue for the number of cycles that the DMC-400 keeps the dfi_wrdata_en signal asserted. If the PHY requires notification of pending write data sooner, you can adjust the tphy_wrdata timing parameter to a higher value.

dfi_wrdata_mask[a]

Output

Write-data byte mask. The timing is the same as for the dfi_wrdata bus. For example, the dfi_wrdata_mask [0] signal defines masking for the dfi_wrdata [7:0] signals, the dfi_wrdata_mask [1] signal defines masking for the dfi_wrdata [15:8] signals. If the dfi_wrdata bus is not a multiple of 8 bits, then the most significant bit of the dfi_wrdata_mask signal corresponds to the most significant partial byte of data.

dfi_wrdata_en[a]

Output

Write data and data mask valid. These signals must be asserted tphy_wrdata cycles before the DMC-400 puts the data and data mask on the DFI interface. If the PHY requires notification of pending write data sooner, you can adjust the tphy_wrdata timing parameter to a higher value. The DMC-400 must send the dfi_wrdata_en signal tphy_wrlat cycles after the write command. When the DMC-400 asserts the dfi_wrdata_en signal, it must keep it asserted for the number of contiguous cycles that the write-data passes through the DFI write-data interface. A DFI term defines the width of the dfi_wrdata_en signal. There must be a single dfi_wrdata_en bit for each slice of memory data.

dfi_wrecc

Output

Write data ECC code bus. It has the same timing as the dfi_wrdata signal.

dfi_wrecc_mask

Output

Write data ECC code byte mask. It has the same timing as the dfi_wrdata_mask signal.

dfi_wrecc_en

Output

Write data ECC code and mask valid. It has the same timing as the dfi_wrdata_en signal.

dfi_dram_clk_disable[a]

Output

DRAM clock disable. When it is active, it indicates to the PHY that the clocks to the DRAM devices must be disabled so that the clock signals hold a constant value. When the dfi_dram_clk_disable signal is inactive, the DRAMs must be clocked normally.

dfi_phyupd_req

Input

PHY-initiated update request. The PHY uses the dfi_phyupd_req signal for a PHY-initiated update. It indicates that the PHY requires the DFI not to send control, read, or write commands or data for a specified period of time. The dfi_phyupd_req signal must remain asserted until both the DMC-400 acknowledges the request by asserting the dfi_phyupd_ack signal, and the update is complete. The DMC-400 must acknowledge this request.

dfi_phyupd_ack

Output

PHY-initiated update acknowledge. The DMC-400 uses the dfi_phyupd_ack signal for a PHY-initiated update. It indicates that the DFI is idle and remains so until the PHY deasserts the dfi_phyupd_req signal. While this signal is asserted, the DFI bus must remain idle except for transactions specifically associated with the update process.

dfi_phyupd_type

Input

PHY-initiated update select. The dfi_phyupd_type signal indicates which one of the 4 types of PHY update times is being requested by the dfi_phyupd_req signal.

dfi_clp_req

Output

Low-power opportunity request. The DMC-400 uses the dfi_clp_req signal to inform an ARM PHY that it can switch to a low-power state.

dfi_clp_ack

Input

Low-power acknowledge. The PHY asserts the dfi_clp_ack signal to acknowledge the DMC-400 low-power opportunity request. The PHY is not required to acknowledge this request. This signal corresponds to command signals and associated logic.

dfi_clp_wakeup

Output

Low-power wakeup time. The dfi_clp_wakeup signal indicates which one of the 16 wakeup times the MC is requesting for the PHY. This signal corresponds to command signals and associated logic.

dfi_rdlp_req

Output

Low-power opportunity request. The DMC-400 uses the dfi_rdlp_req signal to inform the PHY of an opportunity to switch to a low-power state. This signal corresponds to read data signals and associated logic.

dfi_rdlp_ack

Input

Low-power acknowledge. The PHY asserts the dfi_rdlp_ack signal to acknowledge the DMC-400 low-power opportunity request. The PHY is not required to acknowledge this request. This signal corresponds to read data signals and associated logic.

dfi_rdlp_wakeup

Output

Low-power wakeup time. The dfi_rdlp_wakeup signal indicates which one of the 16 wakeup times the MC is requesting for the PHY. This signal corresponds to read data signals and associated logic.

dfi_wrlp_req

Output

Low-power opportunity request. The DMC-400 uses the dfi_wrlp_req signal to inform the PHY of an opportunity to switch to a low-power state. This signal corresponds to write data signals and associated logic.

dfi_wrlp_ack

Input

Low-power acknowledge. The the PHY asserts the dfi_wrlp_ack signal to acknowledge the DMC-400 low-power opportunity request. The PHY is not required to acknowledge this request. This signal corresponds to write data signals and associated logic.

dfi_wrlp_wakeup

Output

Low-power wakeup time. The dfi_wrlp_wakeup signal indicates which one of the 16 wakeup times the DMC-400 is requesting for the PHY. This signal corresponds to write data signals and associated logic.

dfi_rdlvl_req

Input

PHY-initiated read data eye training request.
dfi_rdlvl_cs_nInputPHY-initiated read training chip-select. This indicates which chip is requesting training.

dfi_rdlvl_en

Output

PHY data eye training logic enable. If the PHY initiates the training request, see the dfi_rdlvl_req signal, then the DMC-400 can use dfi_rdlvl_en to acknowledge the training request:

1

Training logic enabled.

0

Normal operation.

The DMC-400 asserts this signal to trigger read training.

dfi_rdlvl_gate_req

Input

PHY-initiated read gate training request.

dfi_rdlvl_gate_en

Output

PHY gate training logic enable. If the PHY initiates the training request, see the dfi_rdlvl_gate_req signal, the DMC-400 uses dfi_rdlvl_gate_en to acknowledge that request:

1

Training logic enabled.

0

Normal operation.

The DMC-400 asserts this signal to initiate read training.

dfi_rdlvl_resp

Input

Read training response. The response definition depends on the mode of operation and the memory type for the system:

PHY Evaluation mode for DDR3 memory systems

The response indicates that the PHY has completed read leveling and centered the DQS relative to the data or placed the gate within the DQS preamble.

PHY Evaluation mode for LPDDR2 memory systems

The response indicates that the PHY has completed data eye training or gate training and centered the DQS relative to the data or placed the gate within the DQS preamble.

dfi_wrlvl_req

Input

PHY-initiated write training request.
dfi_wrlvl_cs_nInputPHY-initiated write training chip-select. This indicates which chip is requesting training.

dfi_wrlvl_en

Output

PHY write training logic enable. If the PHY initiates the training request with the dfi_wrlvl_req signal, then the DMC-400 uses dfi_wrlvl_en to acknowledge that request:

1

Training logic enabled.

0

Normal operation.

The DMC-400 asserts this signal to initiate data eye training.

dfi_wrlvl_strobe

Output

Write training strobe. This triggers the PHY write leveling strobe.

dfi_wrlvl_resp

Input

Write training response for PHY Evaluation mode. The PHY asserts this signal to indicate that it has completed write leveling and aligned the DQS relative to the memory clock.

The DMC-400 uses this value to determine how to adjust the delay value.

dfi_ref_enInput

Configuration tie-off pin for the refresh during training feature:

1

Refresh during training enabled.

0

Normal operation.

[a] Signal width is configuration dependent.


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