A.2. ACE-Lite signals

Table A.2 shows the ACE-Lite signals. See the AMBA AXI and ACE™ Protocol Specification AXI3™, AXI4™, and AXI4-Lite™, ACE and ACE-Lite.

Table A.2. ACE-Lite interface signals

Signal

Type

Description

awid[a]

Input

Write address ID. This signal is the identification tag for the write address group of signals.

awaddr[a]

Input

Write address. The write address bus defines the address of the first transfer of a write burst transaction. The associated control signals determine the addresses of the remaining transfers in the burst.

awregion

Input

Region identifier. Enables a single physical interface on a slave to be used for multiple logical interfaces.

awdomain

Input

This signal indicates the shareability domain of a write transaction. The DMC-400 does not functionally use this signal.

awsnoop

Input

This signal indicates the transaction type for shareable write transactions.

awbar

Input

This signal indicates a write barrier transaction.

awlen

Input

Burst length. The burst length gives the number of transfers in a burst. This information determines the number of data transfers associated with the address.

awsize

Input

Burst size. This signal indicates the size of each transfer in the burst. Byte lane strobes indicate which byte lanes to update.

awburst

Input

Burst type. The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated.

awlock

Input

Lock type. This signal provides additional information about the atomic characteristics of the transfer.

awcache

Input

Cache type. This signal indicates the bufferable, cacheable, write-through, write-back, and allocate attributes of the transaction.

awprot

Input

Protection type. This signal indicates the normal, privileged, or secure protection level of the transaction and whether the transaction is a data access or an instruction access.

awqos

Input

Quality of Service. This signal is used to provide a QoS identifier for each write transaction.

awvalid

Input

Write address valid. This signal indicates that valid write address and control information are available.

awready

Output

Write address ready. This signal indicates that the slave is ready to accept an address and associated control signals.

wdata[a]

Input

Write data.

wstrb[a]

Input

Write strobes. This signal indicates which byte lanes to update in memory.

wlast

Input

Write last. This signal indicates the last transfer in a write burst.

wvalid

Input

Write valid. This signal indicates that valid write data and strobes are available.

wready

Output

Write ready. This signal indicates that the slave can accept the write data.

bid[a]

Output

Response ID. The identification tag of the write response. The bid value must match the awid value of the write transaction to which the slave is responding.

bresp

Output

Write response. This signal indicates the status of the write transaction. The permitted responses are OKAY, EXOKAY, SLVERR, and DECERR.

bvalid

Output

Write response valid. This signal indicates that a valid write response is available.

bready

Input

Response ready. This signal indicates that the master can accept the response information.

arid[a]

Input

Read address ID. This signal is the identification tag for the read address group of signals.

araddr[a]

Input

Read address. The read address bus gives the initial address of a read burst transaction. Only the start address of the burst is provided and the control signals that are issued alongside the address describe how the address is calculated for the remaining transfers in the burst.

arregion

Input

Region decode signal. The signal is provided alongside the transaction address. The signal enables a single physical interface on a slave to be used for multiple logical interfaces that reside in different locations in the system address map.

ardomain

Input

This signal indicates the shareability domain of a read transaction. The DMC-400 does not use this signal functionally.

arsnoop

Input

This signal indicates the transaction type for shareable read transactions.

arbar

Input

This signal indicates a read barrier transaction.

arlen

Input

Burst length. The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.

arsize

Input

Burst size. This signal indicates the size of each transfer in the burst.

arburst

Input

Burst type. The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated.

arlock

Input

Lock type. This signal provides additional information about the atomic characteristics of the transfer.

arcache

Input

Cache type. This signal provides additional information about the cacheable characteristics of the transfer.

arprot

Input

Protection type. This signal provides protection unit information for the transaction.

arqos

Input

Quality of Service. Signal used to provide a QoS identifier for each read transaction.

arvalid

Input

Read address valid. When HIGH this signal indicates that the read address and control information is valid and stable until the arready address acknowledge signal is HIGH.

arready

Output

Read address ready. This signal indicates that the slave is ready to accept an address and associated control signals.

rid[a]

Output

Read ID tag. This signal is the ID tag of the read data group of signals. The rid value is generated by the slave and must match the arid value of the read transaction to which it is responding.

rdata[a]

Output

Read data.

rresp

Output

Read response. This signal indicates the status of the read transfer. The permitted responses are OKAY, EXOKAY, SLVERR, and DECERR.

rlast

Output

Read last. This signal indicates the last transfer in a read burst.

rvalid

Output

Read valid. This signal indicates that the required read data is available and the read transfer can complete.

rready

Input

Read ready. This signal indicates that the master can accept the read data and response information.

[a] Signal width is configuration dependent.


Copyright © 2011-2013 ARM. All rights reserved.ARM DDI 0466E
Non-ConfidentialID120513