A.4. APB signals

Table A.5 shows the APB signals. See the AMBA 3 APB™ Protocol Specification.

Table A.5. APB interface signals

Signal

Type

Description

pclk

Input

Clock. The rising edge of pclk synchronizes all transfers on the APB.

presetn

Input

Reset. The APB reset signal is active LOW. This signal is normally connected directly to the system bus reset signal.

paddr

Input

Address. This is the APB address bus. It can be up to 32-bits wide and is driven by the peripheral bus bridge unit.

psel

Input

Select. The APB bridge unit generates this signal to each peripheral bus slave. It indicates that the slave device is selected and that a data transfer is required.There is a psel signal for each slave.

penable

Input

Enable. This signal indicates the second and subsequent cycles of an APB transfer.

pwrite

Input

Direction. This signal indicates an APB write access when HIGH and an APB read access when LOW.

prdata

Output

Read Data. The selected slave drives this bus during read cycles when pwrite is LOW. This bus can be up to 32-bits wide.

pwdata

Input

Write data. This bus is driven by the peripheral bus bridge unit during write cycles when pwrite is HIGH. This bus can be up to 32-bits wide.

pready

Output

Ready. The slave uses this signal to extend an APB transfer.

pslverr

Output

This signal indicates a transfer failure. APB peripherals are not required to support the pslverr pin. This is true for both existing and new APB peripheral designs. When a peripheral does not include this pin, the appropriate input to the APB bridge is tied LOW.

pclken

Input

This is an optional enable signal for pclk domain.

Copyright © 2011-2013 ARM. All rights reserved.ARM DDI 0466E
Non-ConfidentialID120513