2.2.4. Power control

The DMC-400 and the DRAM have several operating states. Each operating state consumes different amounts of power. The DMC-400 enables you to control its operating state and the operating state of the DRAM. Therefore you can reduce the power consumption of the DMC-400, the PHY, the interface, and the DRAMs by using the following methods:

Hardware-controlled power management

The DMC-400 provides hardware-controlled power-management of each memory interface through the PHY low-power request interface. This interface enables power-management hardware to remove power from idle memory interfaces and associated logic.

Clock frequency adjustment

You can change the DMC-400 clock frequency. See Clocks.

DMC-400 controlled power management

The DMC-400 supports several features to manage the power dissipation of each memory device in the memory subsystem. These programmable features enable the DMC-400 to automatically manage the entry and exit of the DRAM low-power states when the DRAM is idle.

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