3.5.4. ID Register

The ETMIDR characteristics are:

Purpose

Identifies the implementation of the ETM.

Usage constraints

There are no usage constraints.

Configurations

Available in all configurations.

Attributes

This register has the value 0x410CF25x, where x depends on the release version of the macrocell, see the bits[3:0], Implementation revision field in Table 3.11 for more information.

See the register summary in Table 3.1 and Table 3.2.

Figure 3.4 shows the ETMIDR bit assignments.

Figure 3.4. ETMIDR bit assignments

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Table 3.11 shows the ETMIDR bit assignments.

Table 3.11. ETMIDR bit assignments

BitsNameDescription
[31:24]Implementer

Indicates implementer code:

0x41

ARM.

[23:21]- Reserved, RAZ.
[20]Branch packet encoding

Indicates branch packet encoding support:

0

Supports the original branch packet encoding support.

[19] Security Extensions

Indicates ARM architecture Security Extensions support:

1

Supports Security Extensions architecture.

[18]32-bit Thumb instructions

Indicates 32-bit Thumb instructions support:

1

Supports 32-bit Thumb instructions.

[17]-Reserved, RAZ.
[16]

Load PC first

If an LSM[a] load operation with the PC, indicates where in the list the PC is loaded:

0

PC is not loaded first.

[15:12]ARM processor family

Indicates what ARM profile the processor belongs to:

0b1111

The processor family is defined elsewhere.

[11:8]Major version number

Indicates the major version number of the ETM architecture:

0b0010

ETM v3.x.

[7:4]Minor version number

Indicates the minor version number of the ETM architecture:

0b0101

ETM v x.5.

[3:0]Implementation revision

Indicates the implementation revision:

0b0000

r0p0 release of the ETM -A7 macrocell.

[a] See the Embedded Trace Macrocell Architecture Specification for a definition and list of LSM operations.


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