3.5.1. Main Control Register

The ETMCR characteristics are:

Purpose

Controls general operation of the ETM, such as whether tracing is enabled or coprocessor data is traced.

Usage constraints

There are no usage constraints.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 3.1 and Table 3.2.

Figure 3.1 shows the ETMCR bit assignments.

Figure 3.1. ETMCR bit assignments

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Table 3.8 shows the ETMCR bit assignments.

Table 3.8. ETMCR bit assignments

Bits

Name

Description

[31]

-

Reserved, RAZ/WI.
[30]VMID trace enable
0

VMID tracing disable.

1

VMID tracing enable.

The reset value is 0.

[29]-Reserved, RAZ/WI.

[28]

Timestamping enable

0

Timestamping tracing disable.

1

Timestamping tracing enable.

The reset value is 0.

[27:25]

Processor select

If an ETM is shared between multiple processors, selects which processor to trace. For the maximum value permitted, see bits[14:12] of the System Configuration Register. See the Embedded Trace Macrocell Architecture Specification for more information.

To guarantee that the ETM is correctly synchronized to the new processor, you must update these bits as follows:

  1. Set bit[10], ETM programming, and bit[0], ETM power down, to 1.

  2. Change the processor select bits.

  3. Set bit[0], ETM power down, to 0.

  4. Perform other programming required as normal.

The reset value is 0.

[24]Instrumentation resources access controlNot supported, RAZ/WI.
[23]

Disable software writes

Not supported, RAZ/WI.
[22]Disable register writes from the debuggerNot supported, RAZ/WI.
[21]Port size[3]

Use this bit in conjunction with bits[6:4] in this table.

The reset value is 0, corresponding to the 64-bit port size.

[20]Data-only mode

Enables data-only tracing:

0

Instruction trace enabled.

1

Data-only tracing enabled.

The reset value is 0.

[19]

Filter (CPRT)

Use this bit in conjunction with bit[1], the MonitorCPRT bit.

For more information about the Filter Coprocessor Register Transfers (CPRT) in ETMv3.0 and later, see the Embedded Trace Macrocell Architecture Specification.

The reset value is 0.

[18]

Suppress data

Use this bit with bit[7] to suppress data. For more information about data suppression, see the Embedded Trace Macrocell Architecture Specification.

The reset value is 0.

[17:16]

Port mode[1:0]

In conjunction with bit[13], sets the trace port clocking mode. The ETM-A7 macrocell supports only dynamic mode, corresponding to the value 0b000, but you can write other values to these bits, and a read of the register returns the value written. Writing another value to these bits has no effect on the ETM.

bit[11] of the System Configuration Register indicates if these bits are set to select a supported clocking mode.

The reset value is 0b00.

For more information about trace port clocking modes, see the Embedded Trace Macrocell Architecture Specification.

[15:14]

ContextIDsize

Controls Context ID tracing:

0b00

No Context ID tracing.

0b01

Context ID bits[7:0] traced.

0b10

Context ID bits[15:0] traced.

0b11

Context ID bits[31:0] traced.

Note

Only the number of bytes specified is traced even if the new value is larger than this.

The reset value is 0b00.

[13]Port mode[2]

See the description of bits[17:16] in this table.

The reset value is 0.

[12]

Cycle-accurate tracing

Selects cycle-accurate tracing:

1

Include a precise cycle count of executed instructions. This is achieved by adding extra information into the trace, giving cycle counts even when TraceEnable is inactive.

The reset value is 0.

[11]

ETM port selection

Controls an external output, ETMEN:

0

ETMEN is LOW.

1

ETMEN is HIGH.

You can use the ETMEN signal to control the routing of trace port signals to shared GPIO pins on your SoC, under the control of logic external to the ETM.

Trace software tools must set this bit to 1 to ensure that trace output is enabled from this ETM.

The reset value is 0.

[10]

ETM programming

Controls the mode of the ETM:

0

ETM in trace mode.

1

ETM in Programming mode.

For more information about the ETM Programming bit and associated state, see the Embedded Trace Macrocell Architecture Specification.

The reset value is 1.

[9]

Debug request control

Forces the appropriate processor in the Cortex-A7 MPCore device into Debug state:

0

On a trigger event DBGRQ is not set.

1

On a trigger event DBGRQ is set. When a trigger event occurs the DBGRQ output is asserted until the DBACK signal is observed.

The reset value is 0.

[8]

Branch output

Enables the ETM to control the output of all branch addresses, even if the branch results from of a direct branch instruction:

0

Branch addresses not traced.

1

Branch addresses traced. This enables reconstruction of the program flow without having access to the memory image of the code being executed.

The reset value is 0.

[7]

Stall processor

Not supported, RAZ/WI.

[6:4]

Port size[2:0]

In conjunction with bit[21] in this table, Specifies the port size.

The port size determines how many external pins are available to output the trace information on ATDATA[63:0]. The ETM-A7 macrocell supports only the 64-bit port size, corresponding to a Port size[3:0] value of 0b0110, but you can write other values to these bits, and a read of the register returns the value written. Writing other values to these bits has no effect on the ETM.

Bit[10] of the System Configuration Register indicates if these bits are set to select an unsupported port size. See the Embedded Trace Macrocell Architecture Specification for more information.

The reset value is 0b110, corresponding to the 64-bit port size.

[3:2]

Data access

Configures the data tracing mode:

0b00

No data tracing.

0b01

Trace only the data portion of the access.

0b10

Trace only the address portion of the access.

0b11

Trace both the address and the data of the access.

The reset value is 0b00.

[1]

MonitorCPRT

Controls whether CPRTs are traced:

0

CPRTs not traced.

1

CPRTs traced.

This bit is used with bit[19]. For more information about Filter Coprocessor Register Transfers (CPRT) in ETMv3.0 and later. see the Embedded Trace Macrocell Architecture Specification.

The reset value is 0.

[0]

ETM power down

Enables the ETM power to be controlled externally:

0

ETM tracing is enabled.

1

ETM tracing is disabled.

The reset value is 1.

This bit must be cleared by the trace software tools at the beginning of a debug session.

See Control of ETM power down for additional information on controlling ETM power down.


Control of ETM power down

To save power, you can use the ETMPWRUP signal, controlled by the ETM power down bit of the ETMCR, to gate the clock to the logic in the ETM interface of the processor. Also, when you set the ETM power down bit to 1, the clock to most of the logic in the ETM is gated, disabling ETM tracing and leaving the ETM block operating in a low-power mode.

Note

You must not use the ETMEN signal to gate the ETM clock or any other functionality required for basic operation. You can use the ETMEN signal to control functionality that is required only for off-chip tracing, such as multiplexing between two ETMs. Use the ETMPWRUP signal to control basic operation of the ETM.

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