3.4.1. Functional grouping of registers

This section lists the ETM-A7 macrocell registers by functional group as follows:

These functional groups include all of the registers.

Note

All registers are in the CLK clock domain.

General control and ID registers

Table 3.2 shows the general control and ID registers in register number order.

Table 3.2. General control and ID registers

Register numberNameBase offsetDescription
0x000ETMCR0x000Main Control Register
0x001ETMCCR0x004Configuration Code Register
0x003ETMASICCR0x00CASIC Control Register
0x004ETMSR0x010ETM Status Register, see the Embedded Trace Macrocell Architecture Specification
0x005ETMSCR0x014System Configuration Register, see the Embedded Trace Macrocell Architecture Specification
0x00BETMFFLR[a]0x02CFIFOFULL Level Register, see the Embedded Trace Macrocell Architecture Specification
0x078ETMSYNCFR0x1E0Synchronization Frequency Register, see the Embedded Trace Macrocell Architecture Specification
0x079ETMIDR0x1E4ID Register
0x07AETMCCER0x1E8Configuration Code Extension Register
0x07FETMAUXCR0x1FCAuxiliary Control Register
0x080ETMTRACEIDR0x200

CoreSight Trace ID Register, see the Embedded Trace Macrocell Architecture Specification

0x082ETMIDR20x208ETM ID Register 2
0x0C0ETMOSLAR0x300OS Lock Access Register, see the Embedded Trace Macrocell Architecture Specification
0x0C1ETMOSLSR0x304

OS Lock Status Register, see the Embedded Trace Macrocell Architecture Specification

0x0C2ETMOSSRR0x308OS Save and Restore Register, see the Embedded Trace Macrocell Architecture Specification
0x0C4ETMPDCR0x310Power-Down Control Register
0x0C5ETMPDSR 0x314Power-Down Status Register

[a] Although the ETM-A7 macrocell does not include FIFOFULL logic, the FIFOFULL Level Register controls the FIFO level at which data suppression occurs. See the Embedded Trace Macrocell Architecture Specification for more information.


TraceEnable and ViewData registers

Table 3.3 shows the TraceEnable and ViewData registers in register number order.

Table 3.3. TraceEnable and ViewData registers

Register numberNameBase offsetDescription
0x006ETMTSSCR0x018TraceEnable Start/Stop Control Register, see the Embedded Trace Macrocell Architecture Specification
0x007ETMTECR20x01CTraceEnable Control 2 Register, see the Embedded Trace Macrocell Architecture Specification
0x008ETMTEEVR0x020

TraceEnable Event Register, see the Embedded Trace Macrocell Architecture Specification

0x009ETMTECR10x024

TraceEnable Control 1 Register, see the Embedded Trace Macrocell Architecture Specification

0x00CETMVDEVR0x030

ViewData Event Register, see the Embedded Trace Macrocell Architecture Specification

0x00DETMVDCR10x034

ViewData Control 1 Register, see the Embedded Trace Macrocell Architecture Specification

0x00FETMVDCR30x03CViewData Control 3 Register, see the Embedded Trace Macrocell Architecture Specification

Comparator registers

Table 3.4 shows the comparator registers in register number order. These control the address, data, and context ID comparators.

Table 3.4. Comparator registers

Register numberNameBase offsetDescription
0x010-0x017ETMACVR1-80x040-0x05F

Address Comparator Value Registers 1-8, see the Embedded Trace Macrocell Architecture Specification

0x020 to 0x027ETMACTR 1 - 80x080-0x09F

Address Comparator Access Type Registers 1-8, see the Embedded Trace Macrocell Architecture Specification

0x030 [a]ETMDCVR1 [a]0x0C0 [a]

Data Comparator Value Register 1, see the Embedded Trace Macrocell Architecture Specification

0x032 [a]ETMDCVR3[a]0x0C8 [a]Data Comparator Value Register 3, see the Embedded Trace Macrocell Architecture Specification
0x040 [a] ETMDCMR1[a]0x100 [a]

Data Comparator Mask Register 1, see the Embedded Trace Macrocell Architecture Specification

0x042 [a] ETMDCMR3 [a]0x108 [a]Data Comparator Mask Register 3, see the Embedded Trace Macrocell Architecture Specification
0x06CETMCIDCVR10x1B0

Context ID Comparator Value 1 Register, see the Embedded Trace Macrocell Architecture Specification

0x06FETMCIDCMR0x1BCContext ID Comparator Mask Register, see the Embedded Trace Macrocell Architecture Specification
0x090ETMVMIDCVR 0x240

VMID Comparator Value Register, see the Embedded Trace Macrocell Architecture Specification

[a] In the Data Comparator register area, even number registers are reserved. For the ETM-A7 macrocell, reserved areas are:

  • Register 0x031, Data Comparator Value 2, at offset 0x0C4.

  • Register 0x033, Data Comparator Value 4, at offset 0x0CC.

  • Register 0x041, Data Comparator Mask 2, at offset 0x104.

  • Register 0x043, Data Comparator Mask 4, at offset 0x10C.

You must not write to these reserved register addresses. Reads from these addresses is unknown.


Counter, sequencer and other resource registers

Table 3.5 shows the counter, sequencer and other resource registers in register number order. These control:

  • the two counters, and associated events

  • the sequencer, and associated state change events

  • trigger events

  • EXTOUT external output events

  • extended external input selection.

Table 3.5. Counter, sequencer and other resource registers

Register numberNameBase offsetDescription
0x002ETMTRIGGER0x008

Trigger Event Register, see the Embedded Trace Macrocell Architecture Specification

0x050, 0x051ETMCNTRLDEVR1 - 20x140, 0x144

Counter Reload Event Registers 1-2, see the Embedded Trace Macrocell Architecture Specification

0x054, 0x055ETMCNTENR1-20x150, 0x154

Counter Enable Event Registers 1-2, see the Embedded Trace Macrocell Architecture Specification

0x058, 0x059ETMCNTRLDEVR1 - 20x160, 0x164

Counter Reload Event Registers 1-2, see the Embedded Trace Macrocell Architecture Specification

0x05C, 0x05DETMCNTVR1 - 20x170, 0x174

Counter Value Registers, see the Embedded Trace Macrocell Architecture Specification

0x060-0x065ETMSQabEVR0x180 -0x194

Sequencer State Transition Event Registers, see the Embedded Trace Macrocell Architecture Specification

0x067ETMSQR0x19C

Current Sequencer State Register, see the Embedded Trace Macrocell Architecture Specification

0x068, 0x069ETMEXTOUTEVR0x1A0, 0x1A4

External Output Event Registers 1-2, see the Embedded Trace Macrocell Architecture Specification

0x07BETMEXTINSELR0x1ECExtended External Input Selection Register
0x07EETMTSEVR0x1F8

Timestamp Event Register, see the Embedded Trace Macrocell Architecture Specification


CoreSight management registers

Table 3.6 shows the CoreSight management registers in register number order.

Table 3.6. CoreSight management registers

Register numberNameBase offsetDescription
0x3C0ETMITCTRL0xF00

Integration Mode Control Register, see the Embedded Trace Macrocell Architecture Specification

0x3E8ETMCLAIMSET0xFA0Claim Tag Set Register, see the Embedded Trace Macrocell Architecture Specification
0x3E9ETMCLAIMCLR0xFA4Claim Tag Clear Register, see the Embedded Trace Macrocell Architecture Specification
0x3ECETMLAR0xFB0Lock Access Register, see the Embedded Trace Macrocell Architecture Specification
0x3EDETMLSR0xFB4Lock Status Register, see the Embedded Trace Macrocell Architecture Specification
0x3EEETMAUTHSTATUS0xFB8Authentication Status Register, see the Embedded Trace Macrocell Architecture Specification
0x3F2ETMDEVID0xFC8CoreSight Device Configuration Register, see the Embedded Trace Macrocell Architecture Specification
0x3F3ETMDEVTYPE0xFCCCoreSight Device Type Register, see the Embedded Trace Macrocell Architecture Specification
0x3F4-0x3F7Peripheral ID4-ID70xFD0-0xFDCPeripheral identification registers
0x3F8-0x3FBPeripheral ID0-ID30xFE0-0xFEC
0x3FC-0x3FFComponent ID0-ID30xFF0-0xFFCComponent identification registers

Integration test registers

Table 3.7 shows the integration test registers in register number order.

Table 3.7. Integration test registers


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