3.5.13. Integration test registers

The following subsections describe the integration test registers. To access these registers, set bit[0] of the Integration Mode Control Register (ETMITCTRL) to 1.

See the Embedded Trace Macrocell Architecture Specification for more information on ETMITCTRL.

Table 3.20. Output signals that the Integration Test Registers can control

SignalRegisterBitsRegister description
AFREADYITATBCTR0[1]See Integration Test ATB Control Register 0
ATBYTES[2:0]ITATBCTR0[11:9]See Integration Test ATB Control Register 0
ATDATA[63, 55, 47, 39 31, 23, 15, 7, 0]ITATBDATA0[8:0]See Integration Test ATB Data 0 Register
ATID[6:0]ITATBCTR1[6:0]See Integration Test ATB Control Register 1
ATVALIDITATBCTR0[0]See Integration Test ATB Control Register 0
ETMDBGRQITMISCOUT[4]See Integration Test Miscellaneous Outputs register
ETMSTANDBYWFXITMISCOUT[5]See Integration Test Miscellaneous Outputs register
EXTOUT[1:0]ITMISCOUT[9:8]See Integration Test Miscellaneous Outputs register
SYNCREQITATBCTR2[2]See Integration Test ATB Control Register 2
TRIGGERITTRIGGERREQ[0]See Integration Test Trigger Request Register

Table 3.21. Input signals that the Integration Test Registers can read

SignalRegisterBitsRegister description
AFVALIDITATBCTR2[1]See Integration Test ATB Control Register 2
ATREADYITATBCTR2[0]See Integration Test ATB Control Register 2
DBGACKITMISCIN[4]See Integration Test Miscellaneous Input Register
ETMWFXPENDINGITMISCIN[5]See Integration Test Miscellaneous Input Register
EXTIN[3:0]ITMISCIN[3:0]See Integration Test Miscellaneous Input Register

Using the integration test registers

Use the integration test registers to check integration. For example:

When bit[0] of ETMITCTRL is set to 1:

  • Values written to the write-only integration test registers map onto the specified outputs of the macrocell. For example, writing 0x3 to ITMISCOUT[9:8] causes EXTOUT[1:0] to take the value 0x3.

  • Values read from the read-only integration test registers correspond to the values of the specified inputs of the macrocell. For example, if you read ITMISCIN[3:0] you obtain the value of EXTIN[3:0].

When bit[0] of ETMITCTRL is set to 0:

  • Reading an integration test register returns an unpredictable value.

  • The effect of attempting to write to an integration test register, other than the read-only Integration Test Registers, is unpredictable.

    Note

    You must not attempt to write to an integration test register unless you have set bit[0] of ETMITCTRL to 1.

See the Embedded Trace Macrocell Architecture Specification for details of ETMITCTRL.

Integration Test Miscellaneous Outputs register

The ITMISCOUT register characteristics are:

Purpose

Sets the state of the output pins shown in Table 3.22.

Usage constraints
  • Available when bit[0] of ETMITCTRL is set to 1.

  • The value of the register sets the signals on the output pins when the register is written.

Configurations

Available in all configurations.

Attributes

See the register summaries in Table 3.1, Table 3.7, and Table 3.21.

Figure 3.14 shows the ITMISCOUT bit assignments.

Figure 3.14. ITMISCOUT bit assignments

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Table 3.22 shows the ITMISCOUT bit assignments.

Table 3.22. ITMISCOUT bit assignments

BitsNameDescription
[31:10]-Reserved. Write as zero.
[9:8]EXTOUTDrives the EXTOUT[1:0] output pins[a].
[7:6]-Reserved. Write as zero.
[5]ETMWFXREADY

Drives the nETMWFXREADY output pin[a].

[4]ETMDBGRQDrives the ETMDBGRQ output pin[a].
[3:0]-Reserved. Write as zero.

[a] When a bit is set to 0, the corresponding output pin is LOW.

When a bit is set to 1, the corresponding output pin is HIGH.

The ITMISCOUT bit values correspond to the physical state of the output pins.


Integration Test Miscellaneous Input Register

The ITMISCIN Register characteristics are:

Purpose

Reads the state of the input pins shown in Table 3.23.

Usage constraints
  • Available when bit[0] of ETMITCTRL is set to 1.

  • The values of the register bits depend on the signals on the input pins when the register is read.

Configurations

Available in all configurations.

Attributes

See the register summaries in Table 3.1, Table 3.7, and Table 3.21.

Figure 3.15 shows the ITMISCIN bit assignments.

Figure 3.15. ITMISCIN bit assignments

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Table 3.23 shows the ITMISCIN bit assignments.

Table 3.23. ITMISCIN bit assignments

BitsNameDescription
[31:6]-Reserved. Read undefined.
[5]ETMWFXPENDINGReturns the value of the ETMWFXPENDING input pin[a].
[4]DBGACKReturns the value of the DBGACK input pin[a].
[3:0]EXTINReturns the value of the EXTIN[3:0] input pins[a].

[a] When a bit is set to 0, the corresponding input pin is LOW.

When a bit is set to 1, the corresponding input pin is HIGH.

The ITMISCIN bit values always correspond to the physical state of the input pins.


Integration Test Trigger Request Register

The ITTRIGGERREQ Register characteristics are:

Purpose

Sets the TRIGGER output pin shown in Table 3.24.

Usage constraints
  • Available when bit[0] of ETMITCTRL is set to 1.

  • The values of the register bits set the signals on the output pin when the register is written.

Configurations

Available in all configurations.

Attributes

See the register summaries in Table 3.1, Table 3.7, and Table 3.21.

Figure 3.16 shows the ITTRIGGERREQ bit assignments.

Figure 3.16. ITTRIGGERREQ bit assignments

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Table 3.24 shows the ITTRIGGERREQ bit assignments.

Table 3.24. ITTRIGGERREQ bit assignments

BitsNameDescription
[31:1]-Reserved. Write as zero.
[0]TRIGGERDrives the TRIGGER output pin[a].

[a] When a bit is set to 0, the corresponding output pin is LOW.

When a bit is set to 1, the corresponding output pin is HIGH.

The ITTRIGGERREQ bit values always correspond to the physical state of the output pins.


Integration Test ATB Data 0 Register

The ITATBDATA0 Register characteristics are:

Purpose

Sets the state of the ATDATA output pins shown in Table 3.25.

Usage constraints
  • Available when bit[0] of ETMITCTRL is set to 1.

  • The values of the register bits set the signals on the output pins when the register is written.

Configurations

Available in all configurations.

Attributes

See the register summaries in Table 3.1, Table 3.7, and Table 3.21.

Figure 3.17 shows the ITATBDATA0 bit assignments.

Figure 3.17. ITATBDATA0 bit assignments

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Table 3.25 shows the ITATBDATA0 bit assignments.

Table 3.25. ITATBDATA0 bit assignments

BitsNameDescription
[31:9]-Reserved. Write as zero.
[8:0]ATDATADrives the ATDATA[63, 55, 47, 39, 31, 23, 15, 7, 0] output pins[a].

[a] When a bit is set to 0, the corresponding output pin is LOW.

When a bit is set to 1, the corresponding output pin is HIGH.

The ITATBDATA0 bit values always correspond to the physical state of the output pins.


Integration Test ATB Control Register 2

The ITATBCTR2 characteristics are:

Purpose

Reads the state of the AFVALID, ATREADY, and SYNCREQ input pins from the ATB bus, as shown in Table 3.26.

Usage constraints
  • Available when bit[0] of ETMITCTRL is set to 1.

  • The values of the register bits depend on the signals on the input pins when the register is read.

Configurations

Available in all configurations.

Attributes

See the register summaries in Table 3.1, Table 3.7, and Table 3.21.

Figure 3.18 shows the ITATBCTR2 bit assignments.

Figure 3.18. ITATBCTR2 bit assignments

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Table 3.26 shows the ITATBCTR2 bit assignments.

Table 3.26. ITATBCTR2 bit assignments

BitsNameDescription
[31:3]-Reserved. Read undefined.
[2]SYNCREQReturns the value of the SYNCREQ input pin.
[1]AFVALIDReturns the value of the AFVALID input pin[a].
[0]ATREADYReturns the value of the ATREADY input pin[a].

[a] When a bit is set to 0, the corresponding input pin is LOW.

When a bit is set to 1, the corresponding input pin is HIGH.

The ITATBCTR2 bit values always correspond to the physical state of the input pins.


Integration Test ATB Control Register 1

The ITATBCTR1 characteristics are:

Purpose

Sets the state of the ATID output pins shown in Table 3.27.

Usage constraints
  • Available when bit[0] of ETMITCTRL is set to 1.

  • The values of the register bits set the signals on the output pins when the register is written.

Configurations

Available in all configurations.

Attributes

See the register summaries in Table 3.1, Table 3.7, and Table 3.21.

Figure 3.19 shows the ITATBCTR1 bit assignments.

Figure 3.19. ITATBCTR1 bit assignments

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Table 3.27 shows the ITATBCTR1 bit assignments.

Table 3.27. ITATBCTR1 bit assignments

BitsNameDescription
[31:7]-Reserved. Write as zero.
[6:0]ATIDDrives the ATID[6:0] output pins[a].

[a] When a bit is set to 0, the corresponding output pin is LOW.

When a bit is set to 1, the corresponding output pin is HIGH.

The ITATBCTR1 bit values always correspond to the physical state of the output pins.


Integration Test ATB Control Register 0

The ITATBCTR0 characteristics are:

Purpose

Sets the state of the output pins shown in Table 3.28.

Usage constraints
  • Available when bit[0] of ETMITCTRL is set to 1.

  • The values of the register bits set the signals on the output pins when the register is written.

Configurations

Available in all configurations.

Attributes

See the register summaries in Table 3.1, Table 3.7, and Table 3.21.

Figure 3.20 shows the ITATBCTR0 bit assignments.

Figure 3.20. ITATBCTR0 bit assignments

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Table 3.28 shows the ITATBCTR0 bit assignments.

Table 3.28. ITATBCTR0 bit assignments

BitsNameDescription
[31:12]-Reserved. Write as zero.
[11:9]ATBYTESDrives the ATBYTES[2:0] output pins[a].
[8:2]-Reserved. Write as zero.
[1]AFREADYDrives the AFREADY output pin[a].
[0]ATVALIDDrives the ATVALID output pin[a].

[a] When a bit is set to 0, the corresponding output pin is LOW.

When a bit is set to 1, the corresponding output pin is HIGH.

The ITATBCTR0 bit values always correspond to the physical state of the output pins.


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