1.1. About the CoreLink Cache Coherent Interconnect

The CCI-400 combines interconnect and coherency functions into a single module. It supports connectivity for up to two ACE masters, for example, Cortex-A15, and three ACE-Lite masters, for example, Mali-T604, and optional Distributed Virtual Memory (DVM) message support on these interfaces to manage distributed Memory Management Units (MMUs), for example, MMU-400. These can communicate through the CCI-400 with up to three ACE-Lite slaves.

Hardware-managed coherency can improve system performance and reduce system power by sharing on-chip data. Managing coherency has benefits in:

Copyright © 2011-2012 ARM. All rights reserved.ARM DDI 0470D
Non-ConfidentialID040512