CoreLink CCI-400 Cache Coherent Interconnect Technical Reference Manual: 3.3.6. Performance Monitor Control Register (PMCR)

The Performance Monitor Control Register (PMCR) characteristics are:

Table 3.7 shows the bit assignments.

Table 3.7. Performance Monitor Control Register

Bits	Name	Reset Value	Access	Function
[31:16]	-	-	RAZ/WI	Reserved
[15:11]	-	`0x4`	R/WI	Specifies the number of counters implemented
[10:6]	-	-	RAZ/WI	Reserved
[5]	DP	`0x0`	R/W	Disables cycle counter, CCNT, if non-invasive debug is prohibited. The options are as follows: `0b0` Count is not disabled when NIDEN input is LOW. 0b1 Count is disabled when NIDEN input is LOW.
[4]	EX	`0x0`	R/W	Enable export of the events to the event bus, EVNTBUS, for an external monitoring block to trace events. The options are as follows: `0b0` Do not export EVNTBUS. 0b1 Export EVNTBUS.
[3]	CCD	`0x0`	R/W	Cycle count divider. The options are as follows: `0b0` Count every clock cycle when enabled. 0b1 Count every 64^th clock cycle when enabled.
[2]	CCR	`0x0`	RAZ/W	Cycle counter reset. The options are as follows: `0b0` No action. 0b1 Reset cycle counter, CCNT, to zero.
[1]	RST	`0x0`	RAZ/W	Performance counter reset. The options are as follows: `0b0` No action. 0b1 Reset all performance counters to zero, not including CCNT.
[0]	CEN	`0x0`	R/W	Enable bit. The options are as follows: `0b0` Disable all counters, including CCNT. 0b1 Enable all counters including CCNT.

Table 3.8 shows the relationship between the non-invasive debug enable input, NIDEN, and the PMCR register settings.

Table 3.8. Relationship between non-invasive debug enable input, NIDEN, and PMCR register settings

NIDEN input	PMCR.DP	PMCR.EX	Event counters enabled	Events exported	Cycle counter enabled
1	X	0	Yes	No	Yes
1	X	1	Yes	Yes	Yes
0	0	X	No	No	Yes
0	1	X	No	No	No

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