3.3.6. Performance Monitor Control Register (PMCR)

The Performance Monitor Control Register (PMCR) characteristics are:

Purpose

Controls the performance monitor.

Usage constraints

There are no usage constraints.

Configurations

Available in all CCI-400 configurations.

Attributes

Table 3.7 shows the bit assignments.

Table 3.7. Performance Monitor Control Register

BitsNameReset ValueAccessFunction
[31:16]--RAZ/WIReserved
[15:11]-0x4R/WISpecifies the number of counters implemented
[10:6]--RAZ/WIReserved
[5]DP0x0R/W

Disables cycle counter, CCNT, if non-invasive debug is prohibited. The options are as follows:

0b0

Count is not disabled when NIDEN input is LOW.

0b1

Count is disabled when NIDEN input is LOW.

[4]EX0x0R/W

Enable export of the events to the event bus, EVNTBUS, for an external monitoring block to trace events. The options are as follows:

0b0

Do not export EVNTBUS.

0b1

Export EVNTBUS.

[3]CCD0x0R/W

Cycle count divider. The options are as follows:

0b0

Count every clock cycle when enabled.

0b1

Count every 64th clock cycle when enabled.

[2]CCR0x0RAZ/W

Cycle counter reset. The options are as follows:

0b0

No action.

0b1

Reset cycle counter, CCNT, to zero.

[1]RST0x0RAZ/W

Performance counter reset. The options are as follows:

0b0

No action.

0b1

Reset all performance counters to zero, not including CCNT.

[0]CEN0x0R/W

Enable bit. The options are as follows:

0b0

Disable all counters, including CCNT.

0b1

Enable all counters including CCNT.


Table 3.8 shows the relationship between the non-invasive debug enable input, NIDEN, and the PMCR register settings.

Table 3.8. Relationship between non-invasive debug enable input, NIDEN, and PMCR register settings

NIDEN inputPMCR.DPPMCR.EX

Event counters

enabled

Events

exported

Cycle counter

enabled

1X0YesNoYes
1X1YesYesYes
00XNoNoYes
01XNoNoNo

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