3.3.15. Latency Regulation Registers

The Latency Regulation Registers characteristics are:

Purpose

Latency regulation value, AWQOS or ARQOS, scale factor coded for powers of 2 in the range 2-5-2-12, to match a 16-bit integrator. One register exists for each slave interface.

Usage constraints

Accessible using only secure accesses, unless you set the Secure Access Register. See Table 3.4.

Configurations

Only has an effect when QOSOVERRIDE is HIGH for the associated interface.

Attributes

Table 3.17 shows the bit assignments.

Table 3.17. Latency Regulation Register

BitsReset valueAccessFunction
[31:11]-RAZ/WIReserved
[10:8]0x0R/WARQOS scale factor, power of 2 in the range 2-5-2-12
[7:3]-RAZ/WIReserved
[2:0]0x0R/WAWQOS scale factor, power of 2 in the range 2-5-2-12

Table 3.18 shows the mapping of the latency regulation value to the latency regulation scale factor.

Table 3.18. Mapping of latency regulation value to scale factor

Latency regulation

value

Latency regulation

scale factor

0x02-5
0x12-6
0x22-7
0x32-8
0x42-9
0x52-10
0x62-11
0x72-12

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