2.12.1. Clocking

The CCI-400 has a single main clock, ACLK, that is distributed to all sub-blocks. Where masters and slaves connecting to the CCI-400 are in a different clock domain, it is necessary to use external clock-domain-crossing bridges. For more information on hierarchical clock gating, see the CoreLink CCI-400 Cache Coherent Interconnect Integration Manual and CoreLink CCI-400 Cache Coherent Interconnect Implementation Guide.

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