3.4. Address map

The CCI-400 has a global address map, that is, every master has the same view of memory. This is split into 16 regions across the 40-bit address. The decode for each region is determined using a number of CCI-400 inputs that are expected to be static, that is, they are sampled only at reset. The inputs are ADDRMAPx[1:0], where x is an integer from 0-15.

Figure 3.1 shows the CCI-400 address map.

Figure 3.1. Address map

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Table 3.23 shows the decoder mapping.

Table 3.23. Decoder mapping

0b00M0, expected to be connected to the system
0b01M1, expected to be connected to a memory controller
0b10M2, expected to be connected to a memory controller
0b11M1 and M2, striped in 4KB regions, used to load-balance between two memory controllers

The base address for internal CCI-400 registers is defined using a static input, PERIPHBASE[39:15]. The CCI-400 registers are offset by 0x90000 from this base address and occupy an address region of size 64KB.

For example, if PERIPHBASE is 0x0000000, then the register space occupies the following region:

0x0000090000 to 0x000009FFFF.

Accesses within this region, but not to a valid CCI-400 register, generate a DECERR response.

You can only access the CCI-400 register map through the system master interface, M0, so you must configure PERIPHBASE so that the PERIPHBASE to PERIPHBASE + 0x90000 region is within a single region that decodes to M0. An OVL assertion is included to test this assumption.


ARM recommends that PERIPHBASE[39:15] occupies the bottom 4GB address space.

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