3.3.19. Counter Control Registers

The Counter Control Registers characteristics are:

Purpose

Enable or disable the Cycle and Event Counters. One register exists per counter.

Usage constraints

There are no usage constraints.

Configurations

Available in all CCI-400 configurations.

Attributes

Table 3.21 shows the bit assignments.

Table 3.21. Counter Control Register bit assignments

BitsReset valueAccessFunction
[31:1]-RAZ/WIReserved
[0]0x0R/W

Counter enable. The options are as follows:

0b0

Counter disabled.

0b1

Counter enabled.


Copyright © 2011-2012 ARM. All rights reserved.ARM DDI 0470D
Non-ConfidentialID040512