3.3.14. Target Latency Registers

The Target Latency Registers characteristics are:


Determine the target latency, in cycles, for the regulation of reads and writes. A value of 0 corresponds to no regulation. One register exists for each slave interface.

Usage constraints

Accessible using only secure accesses, unless you set the Secure Access Register. See Table 3.4.


Only has an effect when QOSOVERRIDE is HIGH for the associated interface.


Table 3.16 shows the bit assignments.

Table 3.16. Target Latency Register

BitsReset valueAccessFunction
[27:16]0x0R/WAR channel target latency
[11:0]0x0R/WAW channel target latency

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