CoreLink CCI-400 Cache Coherent Interconnect Technical Reference Manual: 3.3.14. Target Latency Registers

CoreLink CCI-400 Cache Coherent Interconnect Technical Reference Manual

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3.3.14. Target Latency Registers

The Target Latency Registers characteristics are:

Purpose: Determine the target latency, in cycles, for the regulation of reads and writes. A value of 0 corresponds to no regulation. One register exists for each slave interface.
Usage constraints: Accessible using only secure accesses, unless you set the Secure Access Register. See Table 3.4.
Configurations: Only has an effect when QOSOVERRIDE is HIGH for the associated interface.
Attributes: See Table 3.1.

Table 3.16 shows the bit assignments.

Table 3.16. Target Latency Register

Bits	Reset value	Access	Function
[31:28]	-	RAZ/WI	Reserved
[27:16]	`0x0`	R/W	AR channel target latency
[15:12]	-	RAZ/WI	Reserved
[11:0]	`0x0`	R/W	AW channel target latency

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