2.11.1. QoS value

Each CCI-400 slave interface has ARQOS and AWQOS input signals that transport a transaction-based QoS value. This determines the relative priority between transactions on that interface, or between interfaces. To gain access to a master interface, each transaction passes through an arbitration point, where it is granted based on the QoS value. Inputs with the same QoS value are arbitrated based on a Least Recently Granted (LRG) scheme.

The NIC-400 Network Interconnect and DMC-400 Dynamic Memory Controller also support arbitration based on QoS value, so the CCI-400 propagates the QoS value on its master interfaces. Transactions that the CCI-400 generates inherit the QoS value from the instigating transaction.


Ensure that you balance the relative priorities of all slave interfaces. For example, setting each to the highest QoS value reduces the arbitration to LRG and no advantage is gained from having a QoS value.

You can override the ARQOS and AWQOS input signals from each slave interface by using a programmable register if the relevant static input signal, QOSOVERRIDE[4:0], with one bit for each of slave interfaces 4-0, is HIGH. The QoS override is either based on a programmable value, or uses latency feedback to set the value within a programmable range.

QoS value based on latency measurement

For applications where a fixed QoS value is not flexible enough for a particular slave interface, the CCI-400 provides a mechanism whereby AxQOS varies depending on the latency measured at that interface. You can program the range of minimum and maximum priority value for each regulator to permit prioritization under worst case conditions. In addition, you can control the rate of change of the regulator by using a programmable scaling factor, Ki.

When you enable latency regulation, the read and write AxQOS values are driven by those generated by the latency monitors. When you disable latency regulation, the input or static values are used, depending on the QoS Override register. The target slave, for example, the DDR controller, should be sensitive to the AxQOS value. That is, a higher priority gives a lower latency.


Turning latency regulation on when QOSOVERRIDE[x] is set LOW for a specific interface has no effect. The AxQOS signals are overridden when QOSOVERRIDE[x] is HIGH.

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