1.4. Interfaces

Figure 1.1 shows an example top-level system using a CCI-400 Cache Coherent Interconnect.

Figure 1.1. Example top-level system using a CCI-400 Cache Coherent Interconnect

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Slave interfaces S4 and S3 support the ACE protocol for connection to masters such as Cortex-A15 processors. Full coherency and sharing of data is managed between these processors.

Slave interfaces S0, S1, S2 support ACE-Lite and DVM signaling for connection to I/O coherent devices such as the Mali-T604 graphics unit. You can use DVM signaling for attached MMUs such as the MMU-400.

You can use the NIC-400 Network Interconnect to connect other masters and peripherals in the system.

The ACE-Lite master interfaces M2 and M1 are optimized for connection to a compatible memory controller such as the DMC-400 Dynamic Memory Controller for DDR2, DDR3, and LPDDR2 memory.

ACE-Lite master interface M0 is designed to connect to the rest of the system.

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