3.1. About this programmers model

The following information applies to the CCI-400 Cache Coherent Interconnect registers:

R/W

Read and write.

RAZ

Read as zero.

WI

Write ignored.

The CCI-400 registers occupy a 64KB region and are offset using the PERIPHBASE[39:15] static input.

The following rules apply:

The programmers view contains regions for control, slave interface, and performance counter registers. See Table 3.1.

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