A.1.2. Configuration signals

Configuration signals are sampled only when ARESETn transitions from LOW to HIGH.

Table A.2 shows the configuration signals.

Table A.2. Configuration signals

SignalDirectionDescription
PERIPHBASE[39:15]InputBase address for CCI-400 programmable registers.[a]
ADDRMAPx[1:0][b]InputDefines the decode of each region of the address map. One set of inputs exists for each of the 16 regions in the address map.
BROADCASTCACHEMAINT[2:0]InputBroadcast cache maintenance operations. One bit exists for each master interface.
BARRIERTERMINATE[2:0]InputTerminate barriers, instead of propagating. One bit exists for each master interface.
BUFFERABLEOVERRIDE[2:0]InputOverride the AWCACHE[0] and ARCACHE[0] outputs to be non-bufferable. One bit exists for each master interface.
QOSOVERRIDE[4:0]InputOverride the ARQOS and AWQOS input signals. One bit exists for each slave interface.
ACCHANNELEN[4:0]InputIf LOW, then AC requests are never issued on the corresponding slave interface. One bit exists for each slave interface.
ECOREVNUM[3:0]InputYou must tie these signals LOW unless you have an Engineering Change Order (ECO) from ARM.

[a] The base address for internal CCI-400 registers is defined using a static input, PERIPHBASE[39:15]. The CCI-400 registers are offset by 0x90000 from this base address, and occupy an address region of size 64KB. For example, if PERIPHBASE is 0x0000000, then the register space occupies the region 0x0000090000 to 0x000009FFFF.

[b] Where x is 0-15.


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