CoreLink CCI-400 Cache Coherent Interconnect Technical Reference Manual: A.1.5. Slave interface signals

A set of slave interface signals exists for each slave interface. The suffix is Sx, where x is 0-4.

This section describes:

Table A.5 shows the write address channel signals.

Table A.5. Write address channel signals

Signal	Direction	Description
AWIDSx[n:0]	Input	Write address ID. You can configure the width of this signal.
AWADDRSx[39:0]	Input	Write address.
AWREGIONSx[3:0]	Input	Write address region. You can tie this signal LOW if the master does not drive it.
AWLENSx[7:0]	Input	Write burst length.
AWSIZESx[2:0]	Input	Write burst size.
AWBURSTSx[1:0]	Input	Write burst type
AWLOCKSx	Input	Write lock type.
AWCACHESx[3:0]	Input	Write cache type.
AWPROTSx[2:0]	Input	Write protection type.
AWSNOOPSx[2:0]	Input	Write snoop request type.
AWDOMAINSx[1:0]	Input	Write domain.
AWBARSx[1:0]	Input	Write barrier type.
AWQOSSx[3:0]	Input	Write Quality-of-Service (QoS) value.
AWUSERSx[n:0]	Input	User-specified extension to AW payload.
AWVALIDSx	Input	Write address valid.
AWREADYSx	Output	Write address ready.

Table A.6 shows the write data channel signals.

Table A.6. Write data channel signals

Signal	Direction	Description
WDATASx[127:0]	Input	Write data
WSTRBSx[15:0]	Input	Write byte-lane strobes
WLASTSx	Input	Write data last transfer indication
WUSERSx[n:0]	Input	User-specified extension to W payload
WVALIDSx	Input	Write data valid
WREADYSx	Output	Write data ready

Table A.7 shows the write data response channel signals.

Table A.7. Write data response channel signals

Signal	Direction	Description
BIDSx[n:0]	Output	Write response ID. You can configure the width.
BRESPSx[1:0]	Output	Write response.
BUSERSx[n:0]	Output	User-specified extension to B payload.
BVALIDSx	Output	Write response valid.
BREADYSx	Input	Write response ready.

Table A.8 shows the read address channel signals.

Table A.8. Read address channel signals

Signal	Direction	Description
ARIDSx[n:0]	Input	Read address ID. You can configure the width of this signal.
ARADDRSx[39:0]	Input	Read address.
ARREGIONSx[3:0]	Input	Read address region. You can tie this signal LOW if the master does not drive it.
ARLENSx[7:0]	Input	Read burst length.
ARSIZESx[2:0]	Input	Read burst size.
ARBURSTSx[1:0]	Input	Read burst type.
ARLOCKSx	Input	Read lock type.
ARCACHESx[3:0]	Input	Read cache type.
ARPROTSx[2:0]	Input	Read protection type.
ARDOMAINSx[1:0]	Input	Read domain.
ARSNOOPSx[3:0]	Input	Read snoop request type.
ARBARSx[1:0]	Input	Read barriers.
ARQOSSx[3:0]	Input	Read QoS.
ARUSERSx[n:0]	Input	User-specified extension to AR payload.
ARVALIDSx	Input	Read address valid.
ARREADYSx	Output	Read address ready.

Table A.9 shows the read data channel signals.

Table A.9. Read data channel signals

Signal	Direction	Description
RIDSx[n:0]	Output	Read data ID. You can configure the width of this signal.
RDATASx[127:0]	Output	Read data.
RRESPSx[3:0]	Output	Read data response for ACE interfaces, that is, S3 and S4.
RRESPSx[1:0]	Output	Read data response for ACE-Lite interfaces, that is, S0, S1, S2.
RLASTSx	Output	Read data last transfer indication.
RUSERSx[n:0]	Output	User-specified extension to R payload.
RVALIDSx	Output	Read data valid.
RREADYSx	Input	Read data ready.

Table A.10 shows the coherency address channel signals.

Table A.10. Coherency address channel signals

Signal	Direction	Description
ACADDRSx[39:0]	Output	Snoop address
ACPROTSx[2:0]	Output	Snoop protection type
ACSNOOPSx[3:0]	Output	Snoop request type
ACVALIDSx	Output	Snoop address valid
ACREADYSx	Input	Master ready to accept snoop address

Table A.11 shows the coherency response channel signals.

Table A.11. Coherency response channel signals

Signal	Direction	Description
CRRESPSx[4:0]	Input	Snoop response
CRVALIDSx	Input	Snoop response valid
CRREADYSx	Output	Slave ready to accept snoop response

Table A.12 shows the coherency data channel signals, for full ACE interfaces, S3 and S4 only.

Table A.12. Coherency data channel signals, full ACE interfaces, S3 and S4 only

Signal	Direction	Description
CDDATASx[127:0]	Input	Snoop data
CDLASTSx	Input	Snoop data last transfer
CDVALIDSx	Input	Snoop data valid
CDREADYSx	Output	Slave ready to accept snoop data

Table A.13 shows the acknowledge signals, full ACE interfaces, S3 and S4 only.

Table A.13. Acknowledge signals, full ACE interfaces, S3 and S4 only

Signal	Direction	Description
RACKSx	Input	Read acknowledge
WACKSx	Input	Write acknowledge

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