2.4.1. Event list

Each event has an 8-bit source code, made up as {source,event}. Each source is allocated a 3-bit code. Table 2.1 shows the 3-bit source code for events.

Table 2.1. 3-bit source code for events

Code[7:5]Source
0x0Slave interface 0, S0
0x1Slave interface 1, S1
0x2Slave interface 2, S2
0x3Slave interface 3, S3
0x4Slave interface 4, S4
0x5Master interface 0, M0
0x6Master interface 1, M1
0x7Master interface 2, M2

The event list that Table 2.2 shows consists of a number of events from slave interfaces and different events from master interfaces.

By default, only events relating to non-secure transactions are recorded. However, if the SPNIDEN input is HIGH, then both secure and non-secure events are counted and exported.

Note

Stall events are not labeled with a security indicator, so are counted irrespective of the SPNIDEN input.

Table 2.2 shows the 5-bit event code event list.

Table 2.2. 5-bit event code event list

Code[4:0]EventValid sources
0x00Read request handshake: any.Slave interface, S0-S4
0x01Read request handshake: device transaction.
0x02Read request handshake: normal, non-shareable or system-shareable, but not barrier or cache maintenance operation.
0x03Read request handshake: inner- or outer-shareable, but not barrier, DVM message or cache maintenance operation.
0x04Read request handshake: cache maintenance operation, CleanInvalid, CleanShared, MakeInvalid.
0x05Read request handshake: memory barrier.
0x06Read request handshake: synchronization barrier.
0x07Read request handshake: DVM message, not synchronization.
0x08Read request handshake: DVM message, synchronization.
0x09Read request stall cycle because the transaction tracker is full. Increase SIx_R_MAX to avoid this stall.
0x0ARead data last handshake: data returned from the snoop instead of from downstream.
0x0BRead data stall cycle: RVALIDS is HIGH, RREADYS is LOW.
0x0CWrite request handshake: any.
0x0DWrite request handshake: device transaction.
0x0EWrite request handshake: normal, non-shareable, or system-shareable, but not barrier.
0x0FWrite request handshake: inner- or outer-shareable, WriteBack or WriteClean.
0x10Write request handshake: WriteUnique.
0x11Write request handshake: WriteLineUnique.
0x12Write request handshake: Evict.
0x13Write request stall cycle because the transaction tracker is full. Increase SIx_W_MAX to avoid this stall.
0x14RETRY of speculative fetch transaction.Master interface, M0-M2
0x15Read request stall cycle because of an address hazard.
0x16Read request stall cycle because of an ID hazard.
0x17Read request stall cycle because the transaction tracker is full. Increase MIx_R_MAX to avoid this stall. See the CoreLink CCI-400 Cache Coherent Interconnect Integration Manual.
0x18Read request stall cycle because of a barrier hazard.
0x19Write request stall cycle because of a barrier hazard.
0x1AWrite request stall cycle because the transaction tracker is full. Increase MIx_W_MAX to avoid this stall. See the CoreLink CCI-400 Cache Coherent Interconnect Integration Manual.

Event bus

The CCI-400 exports a vector of event signals, EVNTBUS, with the bit allocation that Table 2.3 shows.

Table 2.3. EVNTBUS bit allocation

BitsSource
[120:114]AMI2 event bus
[113:107]AMI1 event bus
[106:100]AMI0 event bus
[99:80]ASI4 event bus
[79:60]ASI3 event bus
[59:40]ASI2 event bus
[39:20]ASI1 event bus
[19:0]ASI0 event bus

Table 2.4 shows the bit positions that the ASI events have within each group of signals on the event bus.

Table 2.4. ASIx event bus

OffsetEvent
[19]Write request stall cycle because the transaction tracker is full. Increase SIx_W_MAX to avoid this stall.
[18]Write request handshake: Evict.
[17]Write request handshake: WriteLineUnique.
[16]Write request handshake: WriteUnique.
[15]Write request handshake: inner- or outer-shareable, WriteBack or WriteClean.
[14]Write request handshake: normal, non-shareable, or system-shareable, but not barrier.
[13]Write request handshake: device transaction.
[12]Write request handshake: any.
[11]Read data stall cycle: RVALIDS is HIGH, RREADYS is LOW.
[10]Read data last handshake: data returned from the snoop instead of from downstream.
[9]Read request stall cycle because the transaction tracker is full. Increase SIx_R_MAX to avoid this stall.
[8]Read request handshake: DVM message, synchronization.
[7]Read request handshake: DVM message, non-synchronization.
[6]Read request handshake: synchronization barrier.
[5]Read request handshake: memory barrier.
[4]Read request handshake: cache maintenance operation, CleanInvalid, CleanShared, MakeInvalid.
[3]Read request handshake, inner- or outer-shareable, but not barrier, DVM message or cache maintenance operation.
[2]Read request handshake: normal, non-shareable or system-shareable, but not barrier or cache maintenance operation.
[1]Read request handshake: device transaction.
[0]Read request handshake: any.

Table 2.5 shows the allocation of master interface events.

Table 2.5. AMIx event bus

OffsetEvent
[6]Write request stall cycle, transaction tracker full
[5]Write request stall cycle, barrier hazard
[4]Read request stall cycle, barrier hazard
[3]Read request stall cycle, transaction tracker full
[2]Read request stall cycle, ID hazard
[1]Read request stall cycle, address hazard
[0]Retry of speculative fetch transaction

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