A.1.6. Master interface signals

A set of master interface signals exists for each master interface. The suffix is My, where y is 0, 1, or 2.

This section describes:

Write address channel signals

Table A.14 shows the write address channel signals.

Table A.14. Write address channel signals

AWIDMy[n:0]OutputWrite address ID. Width is the maximum AWID width across the slave interfaces + 3 bits.
AWADDRMy[39:0]OutputWrite address.
AWREGIONMy[3:0]OutputWrite address region.
AWLENMy[7:0]OutputWrite burst length.
AWSIZEMy[2:0]OutputWrite burst size.
AWBURSTMy[1:0]OutputWrite burst type.
AWLOCKMyOutputWrite lock type.
AWCACHEMy[3:0]OutputWrite cache type.
AWPROTMy[2:0]OutputWrite protection type.
AWSNOOPMy[2:0]OutputWrite snoop request type.
AWDOMAINMy[1:0]OutputWrite domain.
AWBARMy[1:0]OutputWrite barrier type.
AWQOSMy[3:0]OutputWrite QoS value.
AWUSERMy[n:0]OutputUser-specified extension to AW payload.
AWVALIDMyOutputWrite address valid.
AWREADYMyInputWrite address ready.

Write data channel signals

Table A.15 shows the write data channel signals.

Table A.15. Write data channel signals

WDATAMy[127:0]OutputWrite data
WSTRBMy[15:0]OutputWrite byte-lane strobes
WLASTMyOutputWrite data last transfer indication
WUSERMy[n:0]OutputUser-specified extension to W payload
WVALIDMyOutputWrite data valid
WREADYMyInputWrite data ready

Write data response channel signals

Table A.16 shows the write data response channel signals.

Table A.16. Write data response channel signals

BIDMy[n:0]InputWrite response ID
BRESPMy[1:0]InputWrite response
BUSERMy[n:0]InputUser-specified extension to B payload
BVALIDMyInputWrite response valid
BREADYMyOutputWrite response ready

Read address channel signals

Table A.17 shows the read address channel signals.

Table A.17. Read address channel signals

ARIDMy[n:0]OutputRead address ID. Width is the maximum ARID width across slave interfaces + 3 bits.
ARADDRMy[39:0]OutputRead address.
ARREGIONMy[3:0]OutputRead address region.
ARLENMy[7:0]OutputRead burst length.
ARSIZEMy[2:0]OutputRead burst size.
ARBURSTMy[1:0]OutputRead burst type.
ARLOCKMyOutputRead lock type.
ARCACHEMy[3:0]OutputRead cache type.
ARPROTMy[2:0]OutputRead protection type.
ARDOMAINMy[1:0]OutputRead domain.
ARSNOOPMy[3:0]OutputRead snoop request type.
ARBARMy[1:0]OutputRead barriers.
ARQOSMy[3:0]OutputRead QoS value.
ARUSERMy[n:0]OutputUser-specified extension to AR payload.
ARVALIDMyOutputRead address valid.
ARREADYMyInputRead address ready.

Read data channel signals

Table A.18 shows the read data channel signals.

Table A.18. Read data channel signals

RIDMy[n:0]InputRead data ID
RDATAMy[127:0]InputRead data
RRESPMy[1:0]InputRead data response
RLASTMyInputRead data last transfer indication
RUSERMy[n:0]InputUser-specified extension to R payload
RVALIDMyInputRead data valid
RREADYMyOutputRead data ready

Power control signals, C-channel

Table A.19 shows the power control signals, C-channel.

Table A.19. Power control signals, C-channel

ACTIVEMyOutputIndicates that the master interface has active transactions. You can use it to gate the clock to downstream components.
CSYSREQInputRequest to disable the ACLK input.
CSYSACKOutputClock disable response.
CACTIVEOutputIndicates that the CCI-400 requires the ACLK input to run.

For information on using the power control signals, see the CoreLink CCI-400 Cache Coherent Interconnect Integration Manual.

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