CoreLink CCI-400 Cache Coherent Interconnect Technical Reference Manual: A.1.6. Master interface signals

A set of master interface signals exists for each master interface. The suffix is My, where y is 0, 1, or 2.

This section describes:

Table A.14 shows the write address channel signals.

Table A.14. Write address channel signals

Signal	Direction	Description
AWIDMy[n:0]	Output	Write address ID. Width is the maximum AWID width across the slave interfaces + 3 bits.
AWADDRMy[39:0]	Output	Write address.
AWREGIONMy[3:0]	Output	Write address region.
AWLENMy[7:0]	Output	Write burst length.
AWSIZEMy[2:0]	Output	Write burst size.
AWBURSTMy[1:0]	Output	Write burst type.
AWLOCKMy	Output	Write lock type.
AWCACHEMy[3:0]	Output	Write cache type.
AWPROTMy[2:0]	Output	Write protection type.
AWSNOOPMy[2:0]	Output	Write snoop request type.
AWDOMAINMy[1:0]	Output	Write domain.
AWBARMy[1:0]	Output	Write barrier type.
AWQOSMy[3:0]	Output	Write QoS value.
AWUSERMy[n:0]	Output	User-specified extension to AW payload.
AWVALIDMy	Output	Write address valid.
AWREADYMy	Input	Write address ready.

Table A.15 shows the write data channel signals.

Table A.15. Write data channel signals

Signal	Direction	Description
WDATAMy[127:0]	Output	Write data
WSTRBMy[15:0]	Output	Write byte-lane strobes
WLASTMy	Output	Write data last transfer indication
WUSERMy[n:0]	Output	User-specified extension to W payload
WVALIDMy	Output	Write data valid
WREADYMy	Input	Write data ready

Table A.16 shows the write data response channel signals.

Table A.16. Write data response channel signals

Signal	Direction	Description
BIDMy[n:0]	Input	Write response ID
BRESPMy[1:0]	Input	Write response
BUSERMy[n:0]	Input	User-specified extension to B payload
BVALIDMy	Input	Write response valid
BREADYMy	Output	Write response ready

Table A.17 shows the read address channel signals.

Table A.17. Read address channel signals

Signal	Direction	Description
ARIDMy[n:0]	Output	Read address ID. Width is the maximum ARID width across slave interfaces + 3 bits.
ARADDRMy[39:0]	Output	Read address.
ARREGIONMy[3:0]	Output	Read address region.
ARLENMy[7:0]	Output	Read burst length.
ARSIZEMy[2:0]	Output	Read burst size.
ARBURSTMy[1:0]	Output	Read burst type.
ARLOCKMy	Output	Read lock type.
ARCACHEMy[3:0]	Output	Read cache type.
ARPROTMy[2:0]	Output	Read protection type.
ARDOMAINMy[1:0]	Output	Read domain.
ARSNOOPMy[3:0]	Output	Read snoop request type.
ARBARMy[1:0]	Output	Read barriers.
ARQOSMy[3:0]	Output	Read QoS value.
ARUSERMy[n:0]	Output	User-specified extension to AR payload.
ARVALIDMy	Output	Read address valid.
ARREADYMy	Input	Read address ready.

Table A.18 shows the read data channel signals.

Table A.18. Read data channel signals

Signal	Direction	Description
RIDMy[n:0]	Input	Read data ID
RDATAMy[127:0]	Input	Read data
RRESPMy[1:0]	Input	Read data response
RLASTMy	Input	Read data last transfer indication
RUSERMy[n:0]	Input	User-specified extension to R payload
RVALIDMy	Input	Read data valid
RREADYMy	Output	Read data ready

Table A.19 shows the power control signals, C-channel.

Table A.19. Power control signals, C-channel

Signal	Direction	Description
ACTIVEMy	Output	Indicates that the master interface has active transactions. You can use it to gate the clock to downstream components.
CSYSREQ	Input	Request to disable the ACLK input.
CSYSACK	Output	Clock disable response.
CACTIVE	Output	Indicates that the CCI-400 requires the ACLK input to run.

For information on using the power control signals, see the CoreLink CCI-400 Cache Coherent Interconnect Integration Manual.

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