2.6.1. Imprecise errors

Table 2.6 shows the errors that are signalled as imprecise. All other sources of error are signalled precisely.


An error is signalled either precisely or imprecisely, but never both.

Table 2.6 shows the imprecise errors.

Table 2.6. Imprecise errors

Transaction causing errorChannel receiving errorImprecise error indicator from
A ReadX snoop that misses in the cache and fetches data from downstreamCRSlave interface receiving the CR response
Distributed Virtual Memory messageCRSlave interface receiving the CR response
Speculative fetch that must be retriedRMaster interface receiving the R response
Write that the CCI-400 generatedBMaster interface receiving the B response
Snoop error or write error for WriteUnique or WriteLineUnique transactions that has been split, but not the last transaction in the split sequenceCR or BMaster interface targeted by WU or WLU

The CCI-400 generates a precise DECERR response in the case of a security violation on a CCI-400 register access. See Imprecise Error Register and Security.

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