CoreLink™ CCI-400 Cache Coherent Interconnect Technical Reference Manual

Revision: r0p4


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Glossary
Conventions
Additional reading
Feedback
Feedback on this product
Feedback on content
1. Introduction
1.1. About the CoreLink Cache Coherent Interconnect
1.2. Compliance
1.2.1. Advanced Microcontroller Bus Architecture
1.3. Features
1.4. Interfaces
1.5. Configurable options
1.6. Test features
1.7. Product documentation, design flow, and architecture
1.7.1. Documentation
1.7.2. Design flow
1.8. Product revisions
2. Functional Description
2.1. About the functions
2.2. Snoop connectivity and control
2.3. Speculative fetches
2.4. Performance Monitoring Unit (PMU)
2.4.1. Event list
2.4.2. PMU registers
2.4.3. Using the PMU
2.5. Security
2.5.1. Internal programmers view
2.5.2. Non-TrustZone-aware masters made secure
2.5.3. Security of master interfaces
2.5.4. Security and the Performance Monitoring Unit (PMU)
2.6. Error responses
2.6.1. Imprecise errors
2.6.2. Errors for WriteUnique and WriteLineUnique
2.7. Cache maintenance operations
2.8. Barriers
2.9. Exclusive accesses
2.10. Distributed Virtual Memory (DVM) messages
2.11. Quality-of-Service (QoS)
2.11.1. QoS value
2.11.2. Regulation based on outstanding transactions
2.11.3. QoS programmable registers
2.12. Clock and reset
2.12.1. Clocking
2.12.2. Reset
3. Programmers Model
3.1. About this programmers model
3.2. Register summary
3.3. Register descriptions
3.3.1. Control Override Register
3.3.2. Speculation Control Register
3.3.3. Secure Access Register
3.3.4. Status Register
3.3.5. Imprecise Error Register
3.3.6. Performance Monitor Control Register (PMCR)
3.3.7. Component and Peripheral ID Registers
3.3.8. Snoop Control Registers
3.3.9. Shareable Override Register
3.3.10. Read Channel QoS Value Override Register
3.3.11. Write Channel QoS Value Override Register
3.3.12. QoS Control Register
3.3.13. Max OT Registers
3.3.14. Target Latency Registers
3.3.15. Latency Regulation Registers
3.3.16. QoS Range Register
3.3.17. Event Select Register (ESR)
3.3.18. Event and Cycle Count Registers
3.3.19. Counter Control Registers
3.3.20. Overflow Flag Status Register
3.4. Address map
A. Signal Descriptions
A.1. Signal descriptions
A.1.1. Clock and reset signals
A.1.2. Configuration signals
A.1.3. Debug signals
A.1.4. DFT signal
A.1.5. Slave interface signals
A.1.6. Master interface signals
B. Revisions

List of Tables

2.1. 3-bit source code for events
2.2. 5-bit event code event list
2.3. EVNTBUS bit allocation
2.4. ASIx event bus
2.5. AMIx event bus
2.6. Imprecise errors
2.7. Errors for WriteUnique and WriteLineUnique
3.1. Register summary
3.2. Control Override Register
3.3. Speculation Control Register
3.4. Secure Access Register
3.5. Status Register
3.6. Imprecise Error Register
3.7. Performance Monitor Control Register
3.8. Relationship between non-invasive debug enable input, NIDEN, and PMCR register settings
3.9. Component and Peripheral ID registers
3.10. Snoop Control Registers
3.11. Shareable Override Register
3.12. Read Channel QoS Value Override Register
3.13. Write Channel QoS Value Override Register
3.14. QoS Control Register
3.15. Max OT Register
3.16. Target Latency Register
3.17. Latency Regulation Register
3.18. Mapping of latency regulation value to scale factor
3.19. QoS Range Register
3.20. Event Select Register
3.21. Counter Control Register bit assignments
3.22. Overflow Flag Status Register
3.23. Decoder mapping
A.1. Clock and reset signals
A.2. Configuration signals
A.3. Debug signals
A.4. DFT signal
A.5. Write address channel signals
A.6. Write data channel signals
A.7. Write data response channel signals
A.8. Read address channel signals
A.9. Read data channel signals
A.10. Coherency address channel signals
A.11. Coherency response channel signals
A.12. Coherency data channel signals, full ACE interfaces, S3 and S4 only
A.13. Acknowledge signals, full ACE interfaces, S3 and S4 only
A.14. Write address channel signals
A.15. Write data channel signals
A.16. Write data response channel signals
A.17. Read address channel signals
A.18. Read data channel signals
A.19. Power control signals, C-channel
B.1. Issue A
B.2. Differences between issue A and issue B
B.3. Differences between issue B and issue C
B.4. Differences between issue C and issue D
B.5. Differences between issue D and issue E

Proprietary Notice

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Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM® in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM® shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Where the term ARM® is used it means “ARM® or any of its subsidiaries as appropriate”.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A16 May 2011First release for r0p0
Revision B07 July 2011First release for r0p1
Revision C16 September 2011First release for r0p2
Revision D12 March 2012First release for r0p3
Revision E13 September 2012First release for r0p4
Copyright © 2011-2012 ARM. All rights reserved.ARM DDI 0470E
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