1.1. About the CoreLink Cache Coherent Interconnect

The CCI-400 combines interconnect and coherency functions into a single module. It supports connectivity for up to two AMBA 4 ACE masters, for example, Cortex®-A15 processor or Cortex-A7 processor, and three AMBA 4 ACE-Lite masters, for example, Mali™-T604. It supports optional Distributed Virtual Memory (DVM) message support on these interfaces to manage distributed Memory Management Units (MMUs), for example, CoreLink MMU-400. These can communicate through the CCI-400 with up to three AMBA 4 ACE-Lite slaves.

Hardware-managed coherency can improve system performance and reduce system power by sharing on-chip data. Managing coherency has the following benefits:

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