3.3.6. Performance Monitor Control Register (PMCR)

The Performance Monitor Control Register (PMCR) characteristics are:

Purpose

Controls the performance monitor.

Usage constraints

There are no usage constraints.

Configurations

Available in all CCI-400 configurations.

Attributes

Figure 3.6 shows the bit assignments.

Figure 3.6. Performance Monitor Register bit assignments

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Table 3.7 shows the bit assignments.

Table 3.7. Performance Monitor Control Register bit assignments

Bits

Name

Reset

Access

Function

[31:16]

-

-

RAZ/WI

Reserved.

[15:11]

-

0x4

R/WI

Specifies the number of counters implemented.

[10:6]

-

-

RAZ/WI

Reserved.

[5]

DP

0b0

RW

Disables cycle counter, CCNT, if non-invasive debug is prohibited:

0b0

Count is not disabled when NIDEN input is LOW.

0b1

Count is disabled when NIDEN input is LOW.

[4]

EX

0b0

RW

Enable export of the events to the event bus, EVNTBUS, for an external monitoring block to trace events:

0b0

Do not export EVNTBUS.

0b1

Export EVNTBUS.

[3]

CCD

0b0

RW

Cycle count divider:

0b0

Count every clock cycle when enabled.

0b1

Count every 64th clock cycle when enabled.

[2]

CCR

0b0

RAZ/W

Cycle counter reset:

0b0

No action.

0b1

Reset cycle counter, CCNT, to zero.

[1]

RST

0b0

RAZ/W

Performance counter reset:

0b0

No action.

0b1

Reset all performance counters to zero, not including CCNT.

[0]

CEN

0b0

RW

Enable bit:

0b0

Disable all counters, including CCNT.

0b1

Enable all counters, including CCNT.


Table 3.8 shows the relationship between the non-invasive debug enable input, NIDEN, and the PMCR register settings.

Table 3.8. Relationship between non-invasive debug enable input, NIDEN, and PMCR register settings

NIDEN input

PMCR.DP

PMCR.EX

Event counters

enabled

Events

exported

Cycle counter

enabled

1

X[a]

0

Yes

No

Yes

1

X[a]

1

Yes

Yes

Yes

0

0

X[a]

No

No

Yes

0

1

X[a]

No

No

No

[a] This can be any value.


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