3.3.20. Overflow Flag Status Register

The Overflow Flag Status Register characteristics are:

Purpose

Contains the state of the overflow flags for the Cycle Count Register and event counters. One register exists for each event counter, and one register exists for the cycle counter.

Usage constraints

There are no usage constraints.

Configurations

Available in all CCI-400 configurations.

Attributes

Figure 3.18 shows the bit assignments.

Figure 3.18. Overflow Flag Status Register bit assignments

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Table 3.22 shows the bit assignments.

Table 3.22. Overflow Flag Status Register bit assignments

Bits

Reset

Access

Function

[31:1]

-

RAZ/WI

Reserved.

[0]

0x0

RW

Event counter and cycle counter overflow flag


When reading this register, any overflow flag that reads as 0 indicates that the counter has not overflowed. An overflow flag that reads as 1 indicates that the counter has overflowed.

When writing to this register, any overflow flag written with a value of 0 is ignored, that is, no change. An overflow flag written with a value of 1 clears the counter overflow flag. The negated counter overflow bits are exported from the CCI-400 on the nEVNTCNTOVERFLOW[4:0] signal. You can use this to trigger interrupts. The MSB corresponds to the cycle count overflow.

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