3.3.14. Regulator Target Registers

The Regulator Target Registers characteristics are:

Purpose

Determines the target, in cycles, for the regulation of reads and writes. The target is either transaction latency or inter-transaction period, depending on the programming of the QoS Control Register.

A value of 0 corresponds to no regulation. One register exists for each slave interface.

Usage constraints

Accessible using only Secure accesses, unless you set the Secure Access Register. See Table 3.4.

Configurations

Only has an effect when QOSOVERRIDE is HIGH for the associated interface.

Attributes

Figure 3.13 shows the bit assignments.

Figure 3.13. Regulator Target Register bit assignments

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Table 3.16 shows the bit assignments.

Table 3.16. Regulator Target Register bit assignments

Bits

Reset

Access

Function

[31:28]

-

RAZ/WI

Reserved.

[27:16]

0x0

RW

AR channel regulator target.

[15:12]

-

RAZ/WI

Reserved.

[11:0]

0x0

RW

AW channel regulator target.


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