1.7.2. Design flow

The CCI-400 Cache Coherent Interconnect is delivered as synthesizable RTL. Before you can use it in a product, it must go through the following processes:


The implementer configures and synthesizes the RTL to produce a hard macrocell.


The integrator connects the implemented design into a SoC. This includes connecting it to a memory system and peripherals.


This is the last process. The system programmer develops the software required to configure and initialize the CCI-400, and tests the required application software.

Each process:

The operation of the final device depends on:

Build configuration

The implementer chooses the options that affect how the RTL source files are pre-processed. These options usually include or exclude logic that affects one or more of the area, maximum frequency, and features of the resulting macrocell. For example, the numbers of outstanding transactions that each master and slave interface supports.

Configuration inputs

The integrator configures some features of the CCI-400 Cache Coherent Interconnect by tying inputs to specific values. These configurations affect the start-up behavior before any software configuration is made. They can also limit the options available to the software. For example, the ACCHANNELEN inputs prevent AC requests from being emitted from an unconnected slave interface.

Software configuration

The programmer configures the CCI-400 Cache Coherent Interconnect by programming particular values into registers. This affects the behavior of the CCI-400, for example, by enabling or disabling speculative fetches.


This manual provides a reference for implementation-defined features that are applicable to build configuration options. Reference to a feature that is included means that the appropriate build and pin configuration options are selected. Reference to an enabled feature means one that has also been configured by software.

Copyright © 2011-2013 ARM. All rights reserved.ARM DDI 0470I