3.1. About this programmers model

The following information applies to the CCI-400 Cache Coherent Interconnect registers:

The CCI-400 registers occupy a 64KB region and are offset using the PERIPHBASE[39:15] static input. PERIPHBASE is a system-level signal that defines the base address of a 64KB region of the physical address space for memory-mapped registers. Different components can co-exist in the system by defining different offsets from PERIPHBASE for their own memory-mapped registers.

The following rules apply:

The programmers view contains regions for control, slave interface, and performance counter registers. See Table 3.1.

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