ARM CoreLink CCI-400 Cache Coherent Interconnect Technical Reference Manual: 2.4.3. Using the PMU

2.4.3. Using the PMU

For each performance and monitor test that you run you can:

Select a maximum of four events that you want to monitor during the test.
Determine the length of the test in terms of clock cycles.
Read the value of each event counter at the end of the test.
Detect if any of the counters overflow.

Use the following registers to set up your test:

For each event that you want to monitor, use the respective:
- Event Select Register to select the event.
- Event Count Register to indicate how many of the events occur.
- Event Counter Control Register to enable or disable the event counter.
- Event Overflow Flag Status Register to detect for overflow of the event counter.
Use the Cycle Count Register to show the number of clock cycles that occur during the test.
Use the Cycle Count Control Register to enable or disable the test.
Use the Cycle Count Overflow Flag Status Register to detect for an overflow.

The following is an example of how you can use the PMU to measure the snoop hit rate for shareable read requests on slave interface 3 and slave interface 4:

Set up the Performance counters as follows:
1. Set up the Event Select Registers (ESRs) as follows:
  - To set ESR0 to count shareable read requests through slave interface 3:
    Program bits[7:5] to 0x3 to select slave interface 3.
    Program bits[4:0] to 0x03 to select the shareable read event.
  - To set ESR1 to count slave interface 3 snoop hits:
    Program bits[7:5] to 0x3.
    Program bits[4:0] to 0x0A.
  - To set ESR2 to count shareable read requests through slave interface 4:
    Program bits[7:5] to 0x4.
    Program bits[4:0] to 0x03.
  - To set ESR3 to count slave interface 4 snoop hits:
    Program bits[7:5] to 0x4.
    Program bits[4:0] to 0x0A.
2. Enable all of the event counters by doing the following:
  - Program Counter Control Register 0 bit[0] to 0b1.
  - Program Counter Control Register 1 bit[0] to 0b1.
  - Program Counter Control Register 2 bit[0] to 0b1.
  - Program Counter Control Register 3 bit[0] to 0b1.
Program the following bits in the Performance Monitor Control Register (PMCR):
- Bits[2:1] to 0b11 to reset the cycle counter and all of the event counters.
- Bit[0] to 0b1 to enable all of the counters.
Allow the test to run for an appropriate amount of time
Do the following to disable all of the counters to stop the test:
- Program PMCR bit[0] to 0b0.
Read the results of the test from the cycle counter and event counters:
- The cycle counter holds the number of clock cycles that the test ran for.
- Counter 0 holds the number of reads for slave interface 3.
- Counter 1 holds the number of snoop hits for slave interface 3.
- Counter 2 holds the number of reads for slave interface 4.
- Counter 3 holds the number of snoop hits for slave interface 4.
Check the overflow bits of all the counters and adjust your results accordingly.

Copyright © 2011-2013 ARM. All rights reserved.	ARM DDI 0470I
Non-Confidential	ID091313
PDF version