1.1. About the CoreLink Cache Coherent Interconnect

The CCI-400 combines interconnect and coherency functions into a single module. It supports connectivity for up to two ACE masters, for example:

The CCI-400 also supports up to three ACE-Lite masters, for example, the ARM Mali™-T600 series Graphics Processor Unit (GPU).

There is optional DVM message support on all these interfaces to manage distributed Memory Management Units (MMUs), for example, the CoreLink MMU-400. These can communicate through the CCI-400 with up to three ACE-Lite slaves.

Hardware-managed coherency can improve system performance and reduce system power by sharing on-chip data. Managing coherency has the following benefits:

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